公开(公告)号：US20140045320A1

公开(公告)日：2014-02-13

申请号：US14059873

申请日：2013-10-22

Applicant: Renesas Electronics Corporation

Inventor： Hiroyuki UCHIYAMA ,  Hiraku CHAKIHARA ,  Teruhisa ICHISE ,  Michimoto KAMINAGA

IPC: H01L21/306 ,  H01L21/78

CPC classification number: H01L23/544 ,  G03F9/7076 ,  H01L21/30625 ,  H01L21/31053 ,  H01L21/76229 ,  H01L21/76819 ,  H01L21/78 ,  H01L22/34 ,  H01L23/585 ,  H01L27/0207 ,  H01L29/78 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a semiconductor IC includes forming grooves in a substrate to define a first dummy region and second dummy regions formed at a scribing area, and third dummy regions and a fourth dummy region formed at a product area. A width of the first dummy region is greater than widths of each of the second and third dummy regions and a width of the fourth dummy region is greater than widths of each of the third dummy regions. A conductor pattern is formed over the first dummy region for optical pattern recognition. The first dummy region is formed under the conductor pattern so the grooves are not formed under the conductor pattern. The second dummy regions are spaced from one another by a predetermined spacing at the scribing area, and the third dummy regions are spaced from one another by a predetermined spacing at the product area.

Abstract translation: 形成半导体IC的方法包括在基板上形成槽，以限定形成在划刻区域的第一虚拟区域和第二虚拟区域，以及形成在产品区域的第三虚拟区域和第四虚拟区域。 第一虚拟区域的宽度大于第二和第三虚拟区域中的每一个的宽度，并且第四虚拟区域的宽度大于每个第三虚拟区域的宽度。 在第一虚拟区域上形成用于光学图案识别的导体图案。 第一虚拟区域形成在导体图案下方，使得沟槽不形成在导体图案之下。 第二虚拟区域在划刻区域处以预定间隔彼此间隔开，并且第三虚拟区域在产品区域处彼此间隔开预定间隔。

公开(公告)号：US20180233568A1

公开(公告)日：2018-08-16

申请号：US15949281

申请日：2018-04-10

Applicant: Renesas Electronics Corporation

Inventor： Katsuhiro UCHIMURA ,  Michimoto KAMINAGA

IPC: H01L29/423 ,  H01L29/78 ,  H01L21/265

Abstract: A semiconductor device with enhanced reliability in which a gate electrode for a trench-gate field effect transistor is formed through a gate insulating film in a trench made in a semiconductor substrate. The upper surface of the gate electrode is in a lower position than the upper surface of the semiconductor substrate in an area adjacent to the trench. A sidewall insulating film is formed over the gate electrode and over the sidewall of the trench. The gate electrode and the sidewall insulating film are covered by an insulating film as an interlayer insulating film.

公开(公告)号：US20170047413A1

公开(公告)日：2017-02-16

申请号：US15338539

申请日：2016-10-31

Applicant: Renesas Electronics Corporation

Inventor： Katsuhiro UCHIMURA ,  Michimoto KAMINAGA

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L21/265

CPC classification number: H01L29/4236 ,  H01L21/26513 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/66348 ,  H01L29/66666 ,  H01L29/7397 ,  H01L29/7827

Abstract: A semiconductor device with enhanced reliability in which a gate electrode for a trench-gate field effect transistor is formed through a gate insulating film in a trench made in a semiconductor substrate. The upper surface of the gate electrode is in a lower position than the upper surface of the semiconductor substrate in an area adjacent to the trench. A sidewall insulating film is formed over the gate electrode and over the sidewall of the trench. The gate electrode and the sidewall insulating film are covered by an insulating film as an interlayer insulating film.

Abstract translation: 具有增强的可靠性的半导体器件，其中沟槽栅极场效应晶体管的栅电极通过在半导体衬底中制成的沟槽中的栅极绝缘膜形成。 栅电极的上表面位于与沟槽相邻的区域中比半导体衬底的上表面低的位置。 侧壁绝缘膜形成在栅电极上方和沟槽的侧壁上方。 栅电极和侧壁绝缘膜被作为层间绝缘膜的绝缘膜覆盖。

公开(公告)号：US20150311220A1

公开(公告)日：2015-10-29

申请号：US14679056

申请日：2015-04-06

Applicant: Renesas Electronics Corporation

Inventor： Shigeya TOYOKAWA ,  Michimoto KAMINAGA ,  Kentaro YAMADA

IPC: H01L27/115 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3105 ,  G11C16/12 ,  H01L21/02 ,  H01L21/28 ,  G11C16/14 ,  G11C16/08 ,  G11C16/26 ,  H01L29/788 ,  H01L21/311

CPC classification number: G11C16/12 ,  G11C16/08 ,  G11C16/14 ,  G11C16/26 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/28167 ,  H01L21/28273 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/31053 ,  H01L21/31111 ,  H01L27/11524 ,  H01L27/11531 ,  H01L27/11558 ,  H01L29/7883

Abstract: To enhance the write speed of a nonvolatile memory. A charge injection/emission part of a nonvolatile memory cell includes an active region having an upper face, a side wall, and a shoulder part connecting the upper face and the side wall, a conductor film covering the upper face and the shoulder part of the active region, and a capacitance insulating film provided between the conductor film and the active region. Furthermore, the active region has a protrusion part constituted of a first concave part with respect to the upper face and a second concave part with respect to the side wall, in the shoulder part.

Abstract translation: 提高非易失性存储器的写入速度。 非易失性存储单元的电荷注入/发射部分包括具有上表面，侧壁和连接上表面和侧壁的肩部的有源区，覆盖上表面和侧壁的上表面和肩部的导体膜 有源区和设置在导体膜和有源区之间的电容绝缘膜。 此外，有源区具有在肩部中由相对于上表面的第一凹部和相对于侧壁的第二凹部构成的突出部。

公开(公告)号：US20150279788A1

公开(公告)日：2015-10-01

申请号：US14739818

申请日：2015-06-15

Applicant: Renesas Electronics Corporation

Inventor： Hiroyuki UCHIYAMA ,  Hiraku CHAKIHARA ,  Teruhisa ICHISE ,  Michimoto KAMINAGA

IPC: H01L23/544 ,  H01L23/58 ,  H01L27/02 ,  H01L29/78

CPC classification number: H01L23/544 ,  G03F9/7076 ,  H01L21/30625 ,  H01L21/31053 ,  H01L21/76229 ,  H01L21/76819 ,  H01L21/78 ,  H01L22/34 ,  H01L23/585 ,  H01L27/0207 ,  H01L29/78 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor substrate includes scribe and product regions, with grooves formed in the scribe region. The grooves are embedded with an insulating film to provide an isolation region, and an active region, including semiconductor elements, is formed in the product region. Dummy patterns are formed in the scribe region, which include a first dummy pattern and second dummy patterns for preventing dishing of the insulating film. The second dummy patterns are surrounded and defined by the isolation region. A target pattern for optical pattern recognition is arranged over the first dummy pattern, and includes a first conductive film. A plane area of the first dummy pattern is larger than a plane area of each of the second dummy patterns, and the first dummy pattern and the second dummy patterns are arranged in order from an edge of the semiconductor substrate toward the product region.

Abstract translation: 半导体衬底包括划线和产品区域，在刻划区域中形成有沟槽。 凹槽嵌入绝缘膜以提供隔离区域，并且在产品区域中形成包括半导体元件的有源区域。 在划线区域中形成有虚拟图案，其包括第一虚设图案和用于防止绝缘膜的凹陷的第二虚设图案。 第二虚拟图案由隔离区域包围和限定。 用于光学图案识别的目标图案被布置在第一虚设图案之上，并且包括第一导电膜。 第一虚设图形的平面区域大于第二虚设图案的平面面积，第一虚设图案和第二虚设图案从半导体衬底的边缘朝向产品区域的顺序排列。