公开(公告)号：US20150380382A1

公开(公告)日：2015-12-31

申请号：US14850617

申请日：2015-09-10

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Satoshi UNO ,  Hideaki TSUCHIYA ,  Shinji YOKOGAWA

IPC: H01L23/00 ,  H01L23/498

CPC classification number: H01L24/81 ,  H01L21/76841 ,  H01L23/49811 ,  H01L23/49866 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05099 ,  H01L2224/05186 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05647 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11472 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13611 ,  H01L2224/14133 ,  H01L2224/14135 ,  H01L2224/14136 ,  H01L2224/14177 ,  H01L2224/16058 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2224/814 ,  H01L2224/81447 ,  H01L2224/81801 ,  H01L2224/94 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2924/2064 ,  H01L2924/3656 ,  H01L2924/04941 ,  H01L2924/01047 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2224/13099 ,  H01L2224/05599 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A semiconductor chip SC includes an electrode pad PAD. A Cu pillar PIL is formed on the electrode pad PAD. In addition, an interconnect substrate INT includes a connection terminal TER. The connection terminal TER contains Cu. For example, the connection terminal TER is formed of Cu, and is formed, for example, in a land shape. However, the connection terminal TER may not be formed in a land shape. The Cu pillar PIL and the connection terminal TER are connected to each other through a solder layer SOL. The solder layer SOL contains Sn. A Ni layer NIL is formed on either the Cu pillar PIL or the connection terminal TER. The minimum value L of the thickness of the solder layer SOL is equal to or less than 20 μm.

Abstract translation: 半导体芯片SC包括电极焊盘PAD。 在电极焊盘PAD上形成Cu柱PIL。 此外，互连基板INT包括连接端子TER。 连接端子TER含有Cu。 例如，连接端子TER由Cu形成，例如形成为平面形状。 然而，连接端子TER可以不形成为平面形状。 Cu柱PIL和连接端子TER通过焊料层SOL彼此连接。 焊料层SOL含有Sn。 在Cu柱PIL或连接端子TER上形成Ni层NIL。 焊料层SOL的厚度的最小值L等于或小于20μm。

公开(公告)号：US20180294239A1

公开(公告)日：2018-10-11

申请号：US15888846

申请日：2018-02-05

Applicant: Renesas Electronics Corporation

Inventor： Kenji SAKATA ,  Toshihiko AKIBA ,  Takuo FUNAYA ,  Hideaki TSUCHIYA ,  Yuichi YOSHIDA

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498

Abstract: There is a need to improve reliability of the semiconductor device.A semiconductor device includes a printed circuit board and a semiconductor chip mounted over the printed circuit board. The semiconductor chip includes a pad, an insulation film including an opening to expose part of the pad, and a pillar electrode formed over the pad exposed from the opening. The printed circuit board includes a terminal and a resist layer including an opening to expose part of the terminal. The pillar electrode of the semiconductor chip and the terminal of the printed circuit board are coupled via a solder layer. Thickness h1 of the pillar electrode is measured from the upper surface of the insulation film. Thickness h2 of the solder layer is measured from the upper surface of the resist layer. Thickness h1 is greater than or equal to a half of thickness h2 and is smaller than or equal to thickness h2.

公开(公告)号：US20130221520A1

公开(公告)日：2013-08-29

申请号：US13781496

申请日：2013-02-28

Applicant: Renesas Electronics Corporation

Inventor： Satoshi UNO ,  Hideaki TSUCHIYA ,  Shinji YOKOGAWA

IPC: H01L21/768 ,  H01L23/498

CPC classification number: H01L24/81 ,  H01L21/76841 ,  H01L23/49811 ,  H01L23/49866 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05099 ,  H01L2224/05186 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05647 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11472 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13611 ,  H01L2224/14133 ,  H01L2224/14135 ,  H01L2224/14136 ,  H01L2224/14177 ,  H01L2224/16058 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2224/814 ,  H01L2224/81447 ,  H01L2224/81801 ,  H01L2224/94 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2924/2064 ,  H01L2924/3656 ,  H01L2924/04941 ,  H01L2924/01047 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2224/13099 ,  H01L2224/05599 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A semiconductor chip SC includes an electrode pad PAD. A Cu pillar PIL is formed on the electrode pad PAD. In addition, an interconnect substrate INT includes a connection terminal TER. The connection terminal TER contains Cu. For example, the connection terminal TER is formed of Cu, and is formed, for example, in a land shape. However, the connection terminal TER may not be formed in a land shape. The Cu pillar PIL and the connection terminal TER are connected to each other through a solder layer SOL. The solder layer SOL contains Sn. A Ni layer NIL is formed on either the Cu pillar PIL or the connection terminal TER. The minimum value L of the thickness of the solder layer SOL is equal to or less than 20 μm.

Abstract translation: 半导体芯片SC包括电极焊盘PAD。 在电极焊盘PAD上形成Cu柱PIL。 此外，互连基板INT包括连接端子TER。 连接端子TER含有Cu。 例如，连接端子TER由Cu形成，例如形成为平面形状。 然而，连接端子TER可以不形成为平面形状。 Cu柱PIL和连接端子TER通过焊料层SOL彼此连接。 焊料层SOL含有Sn。 在Cu柱PIL或连接端子TER上形成Ni层NIL。 焊料层SOL的厚度的最小值L等于或小于20μm。

公开(公告)号：US20230067226A1

公开(公告)日：2023-03-02

申请号：US17847952

申请日：2022-06-23

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Naohito SUZUMURA ,  Hiromichi TAKAOKA ,  Kenichiro SONODA ,  Hideaki TSUCHIYA ,  Yasutaka NAKASHIBA

IPC: H01L23/525 ,  H01L23/522 ,  H01L27/01 ,  H01C7/00

Abstract: An electric fuse element has a first portion, a second portion arranged on one end of the first portion, and a third portion arranged on the other end of the first portion. A resistor element is arranged separately from the electric fuse element. A material of each of the electric fuse element and the resistor element has silicon metal or nickel chromium. The electric fuse element and the resistor element are arranged in an upper layer of the first wiring and in lower layer of the second wiring. A wiring width of the second portion and a wiring width of the third portion are larger than a wiring width of the first portion.

公开(公告)号：US20230061976A1

公开(公告)日：2023-03-02

申请号：US17841203

申请日：2022-06-15

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Naohito SUZUMURA ,  Kenichiro SONODA ,  Hideaki TSUCHIYA

IPC: H01L23/525

Abstract: An interlayer dielectric layer covers an electric fuse element. A resistance layer made of silicon metal is arranged on the interlayer dielectric layer and directly above the electric fuse element.

公开(公告)号：US20220020604A1

公开(公告)日：2022-01-20

申请号：US16930106

申请日：2020-07-15

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hideaki TSUCHIYA ,  Akira MATSUMOTO

IPC: H01L21/56 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00

Abstract: A semiconductor device includes a package substrate, a semiconductor chip and a solder bump. The semiconductor chip is disposed on the package substrate. The package substrate includes a first electrode pad, and a first insulating film formed such that the first insulating film exposes a first portion of a surface of the first electrode pad. The semiconductor chip includes a second electrode pad and a second insulating film formed such that the second insulating film exposes a second portion of a surface of the second electrode pad. The second electrode pad is formed on the first electrode pad through the solder bump. L2/L1 is 0.63 or more in a cross section passing through the first electrode pad, the solder bump and the second electrode pad. A first length of the first portion and a second length of the second portion are defined as L1 and L2, respectively.

公开(公告)号：US20190237421A1

公开(公告)日：2019-08-01

申请号：US16223694

申请日：2018-12-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hideaki TSUCHIYA

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0345 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/0508 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05186 ,  H01L2224/05558 ,  H01L2224/05562 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/10145 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13005 ,  H01L2224/13076 ,  H01L2224/1308 ,  H01L2224/13084 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13118 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16058 ,  H01L2224/16157 ,  H01L2224/16237 ,  H01L2224/16503 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81411 ,  H01L2224/81455 ,  H01L2224/8181 ,  H01L2224/81815 ,  H01L2224/81825 ,  H01L2224/83104 ,  H01L2924/014 ,  H01L2924/3656 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/206 ,  H01L2924/04941 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01049 ,  H01L2924/01083

Abstract: A semiconductor device includes a pad electrode formed over a semiconductor substrate, a conductor pillar formed on the pad electrode, a cap film formed on the conductor pillar and made of a nickel film, a terminal formed in a wiring board, a metal film formed on the terminal and made of a nickel film containing phosphorus, a solder layer interposed between the cap film and the metal film and containing tin as a main component, and an alloy layer interposed between the solder layer and the metal film and containing tin and copper.