公开(公告)号：US09805950B2

公开(公告)日：2017-10-31

申请号：US15462583

申请日：2017-03-17

Applicant: Renesas Electronics Corporation

Inventor： Takuo Funaya ,  Takayuki Igarashi

IPC: H01L29/76 ,  H01L21/3205 ,  H01L23/522 ,  H01L49/02 ,  H01L27/06 ,  H01L21/66 ,  H01L23/00 ,  H01L21/02

CPC classification number: H01L21/3205 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02271 ,  H01L22/14 ,  H01L22/32 ,  H01L23/49575 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/5283 ,  H01L24/03 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L27/06 ,  H01L27/0617 ,  H01L27/0688 ,  H01L28/10 ,  H01L2223/6655 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/45099 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48465 ,  H01L2224/49113 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/12041 ,  H01L2924/1306 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/01015

Abstract: A method of manufacturing a semiconductor device including: (a) forming a first insulation film on a semiconductor substrate; (b) forming a first coil on the first insulation film; (c) forming a second insulation film on the first insulation film so as to cover the first coil; (d) forming a first pad on the second insulation film at a position not overlapped with the first coil in a planar view; (e) forming a laminated insulation film on the second insulation film, the laminated insulation film having a first opening from which the first pad is exposed; and (f) forming a second coil and a first wiring on the laminated insulation film, wherein the second coil is disposed above the first coil, the first coil and the second coil are not connected by a conductor but magnetically coupled to each other, the first wiring is formed from an upper portion of the first pad to an upper portion of the laminated insulation film and is electrically connected to the first pad, and the laminated insulation film includes a silicon oxide film, a silicon nitride film on the silicon oxide film, and a resin film on the silicon nitride film.

公开(公告)号：US10916500B2

公开(公告)日：2021-02-09

申请号：US16523685

申请日：2019-07-26

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tomohiko Aika ,  Takayuki Igarashi ,  Takehiro Ochi

IPC: H01L23/525 ,  H01L21/8234 ,  H01L27/06

Abstract: Reliability of a semiconductor device is improved. The semiconductor device includes a silicon pattern for a fuse element, a metal silicide layer formed on an upper surface and a side surface of the silicon pattern, a gate electrode for MISFET, and a metal silicide layer formed on an upper surface of the gate electrode. The height from the lower surface of the silicon pattern to the lower end of the metal silicide layer is lower than the height from the lower surface of the gate electrode to the lower end of the metal silicide layer.

公开(公告)号：US10483199B2

公开(公告)日：2019-11-19

申请号：US16048408

申请日：2018-07-30

Applicant: Renesas Electronics Corporation

Inventor： Takayuki Igarashi ,  Takuo Funaya

IPC: H01L27/08 ,  H01L23/522 ,  H01L27/06 ,  H01L27/12 ,  H01L23/00 ,  H01L23/495 ,  H01L23/528 ,  H01L23/532 ,  H01L25/16

Abstract: Characteristics of a semiconductor device are improved. A semiconductor device includes a coil CL1 and a wiring M2 formed on an interlayer insulator IL2, a wiring M3 formed on an interlayer insulator IL3, and a coil CL2 and a wiring M4 formed on the interlayer insulator IL4. Moreover, a distance DM4 between the coil CL2 and the wiring M4 is longer than a distance DM3 between the coil CL2 and the wiring M3 (DM4>DM3). Furthermore, the distance DM3 between the coil CL2 and the wiring M3 is set to be longer than a sum of a film thickness of the interlayer insulator IL3 and a film thickness of the interlayer insulator IL4, which are positioned between the coil CL1 and the coil CL2. In this manner, it is possible to improve an insulation withstand voltage between the coil CL2 and the wiring M4 or the like, where a high voltage difference tend to occur. Moreover, a transformer formation region 1A and a seal ring formation region 1C surrounding a peripheral circuit formation region 1B are formed so as to improve the moisture resistance.

公开(公告)号：US10062642B2

公开(公告)日：2018-08-28

申请号：US15616151

申请日：2017-06-07

Applicant: Renesas Electronics Corporation

Inventor： Takayuki Igarashi ,  Takuo Funaya

IPC: H01L27/08 ,  H01L23/522 ,  H01L25/16 ,  H01L23/495 ,  H01L23/528 ,  H01L27/06 ,  H01L27/12 ,  H01L23/00 ,  H01L23/532

CPC classification number: H01L23/5227 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49575 ,  H01L23/5283 ,  H01L23/53214 ,  H01L23/53223 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/167 ,  H01L27/0688 ,  H01L27/1203 ,  H01L2224/02166 ,  H01L2224/05554 ,  H01L2224/45124 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2924/13055 ,  H01L2924/00 ,  H01L2924/00014

Abstract: Characteristics of a semiconductor device are improved. A semiconductor device includes a coil CL1 and a wiring M2 formed on an interlayer insulator IL2, a wiring M3 formed on an interlayer insulator IL3, and a coil CL2 and a wiring M4 formed on the interlayer insulator IL4. Moreover, a distance DM4 between the coil CL2 and the wiring M4 is longer than a distance DM3 between the coil CL2 and the wiring M3 (DM4>DM3). Furthermore, the distance DM3 between the coil CL2 and the wiring M3 is set to be longer than a sum of a film thickness of the interlayer insulator IL3 and a film thickness of the interlayer insulator IL4, which are positioned between the coil CL1 and the coil CL2. In this manner, it is possible to improve an insulation withstand voltage between the coil CL2 and the wiring M4 or the like, where a high voltage difference tend to occur. Moreover, a transformer formation region 1A and a seal ring formation region 1C surrounding a peripheral circuit formation region 1B are formed so as to improve the moisture resistance.

公开(公告)号：US20180061662A1

公开(公告)日：2018-03-01

申请号：US15789740

申请日：2017-10-20

Applicant: Renesas Electronics Corporation

Inventor： Takuo FUNAYA ,  Takayuki Igarashi

IPC: H01L21/3205 ,  H01L21/02 ,  H01L21/66 ,  H01L27/06 ,  H01L23/522 ,  H01L23/00 ,  H01L49/02 ,  H01L23/528 ,  H01L23/495

CPC classification number: H01L21/3205 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02271 ,  H01L22/14 ,  H01L22/32 ,  H01L23/49575 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/5283 ,  H01L24/03 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L27/06 ,  H01L27/0617 ,  H01L27/0688 ,  H01L28/10 ,  H01L2223/6655 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/45099 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48465 ,  H01L2224/49113 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/12041 ,  H01L2924/1306 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/01015

Abstract: A semiconductor device including: a semiconductor substrate; a first coil formed on the semiconductor substrate via a first insulation film; a second insulation film formed on the semiconductor substrate so as to cover the first insulation film and the first coil; a first pad formed on the second insulation film and disposed at a position not overlapped with the first coil in a planar view; a laminated insulation film formed on the second insulation film, the laminated insulation film having a first opening from which the first pad is exposed; a second coil formed on the laminated insulation film and disposed above the first coil; and a first wiring formed on the laminated insulation film including an upper portion of the first pad exposed from the first opening, the first wiring being electrically connected to the first pad.

公开(公告)号：US09653396B2

公开(公告)日：2017-05-16

申请号：US14777454

申请日：2013-03-25

Applicant: Renesas Electronics Corporation

Inventor： Takuo Funaya ,  Takayuki Igarashi

IPC: H01L29/00 ,  H01L23/522 ,  H01L23/00 ,  H01L27/06 ,  H01L21/66 ,  H01L21/3205 ,  H01L49/02 ,  H01L23/528 ,  H01L23/495

CPC classification number: H01L21/3205 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02271 ,  H01L22/14 ,  H01L22/32 ,  H01L23/49575 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/5283 ,  H01L24/03 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L27/06 ,  H01L27/0617 ,  H01L27/0688 ,  H01L28/10 ,  H01L2223/6655 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/45099 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48465 ,  H01L2224/49113 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/12041 ,  H01L2924/1306 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/01015

Abstract: A coil CL1 is formed on a semiconductor substrate SB via a first insulation film, a second insulation film is formed so as to cover the first insulation film and the coil CL1, and a pad PD1 is formed on the second insulation film. A laminated film LF having an opening OP1 from which the pad PD1 is partially exposed is formed on the second insulation film, and a coil CL2 is formed on the laminated insulation film. The coil CL2 is disposed above the coil CL1, and the coil CL2 and the coil CL1 are magnetically coupled to each other. The laminated film LF is composed of a silicon oxide film LF1, a silicon nitride film LF2 thereon, and a resin film LF3 thereon.

公开(公告)号：US20160027732A1

公开(公告)日：2016-01-28

申请号：US14418116

申请日：2014-01-29

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takayuki Igarashi ,  Takuo Funaya

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L25/16

CPC classification number: H01L23/5227 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49575 ,  H01L23/5283 ,  H01L23/53214 ,  H01L23/53223 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/167 ,  H01L27/0688 ,  H01L27/1203 ,  H01L2224/02166 ,  H01L2224/05554 ,  H01L2224/45124 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2924/13055 ,  H01L2924/00 ,  H01L2924/00014

Abstract: Characteristics of a semiconductor device are improved. A semiconductor device includes a coil CL1 and a wiring M2 formed on an interlayer insulator IL2, a wiring M3 formed on an interlayer insulator IL3, and a coil CL2 and a wiring M4 formed on the interlayer insulator IL4. Moreover, a distance DM4 between the coil CL2 and the wiring M4 is longer than a distance DM3 between the coil CL2 and the wiring M3 (DM4>DM3). Furthermore, the distance DM3 between the coil CL2 and the wiring M3 is set to be longer than a sum of a film thickness of the interlayer insulator IL3 and a film thickness of the interlayer insulator IL4, which are positioned between the coil CL1 and the coil CL2. In this manner, it is possible to improve an insulation withstand voltage between the coil CL2 and the wiring M4 or the like, where a high voltage difference tend to occur. Moreover, a transformer formation region 1A and a seal ring formation region 1C surrounding a peripheral circuit formation region 1B are formed so as to improve the moisture resistance.

Abstract translation: 提高了半导体器件的特性。 半导体器件包括形成在层间绝缘体IL2上的线圈CL1和形成在层间绝缘体IL2上的布线M2，形成在层间绝缘体IL3上的布线M3，以及形成在层间绝缘体IL4上的线圈CL2和布线M4。 此外，线圈CL2和布线M4之间的距离DM4比线圈CL2和布线M3之间的距离DM3（DM4> DM3）长。 此外，线圈CL2和布线M3之间的距离DM3被设定为长于位于线圈CL1和线圈之间的层间绝缘体IL3的膜厚和层间绝缘体IL4的膜厚之和 CL2。 以这种方式，可以提高线圈CL2和布线M4之间的绝缘耐受电压，其中趋于发生高电压差。 此外，形成了包围周边电路形成区域1B的变压器形成区域1A和密封环形成区域1C，以提高耐湿性。

公开(公告)号：US10128125B2

公开(公告)日：2018-11-13

申请号：US15789740

申请日：2017-10-20

Applicant: Renesas Electronics Corporation

Inventor： Takuo Funaya ,  Takayuki Igarashi

IPC: H01L29/00 ,  H01L21/3205 ,  H01L23/522 ,  H01L23/00 ,  H01L27/06 ,  H01L21/66 ,  H01L49/02 ,  H01L21/02 ,  H01L23/528 ,  H01L23/495

Abstract: A semiconductor device including: a semiconductor substrate; a first coil formed on the semiconductor substrate via a first insulation film; a second insulation film formed on the semiconductor substrate so as to cover the first insulation film and the first coil; a first pad formed on the second insulation film and disposed at a position not overlapped with the first coil in a planar view; a laminated insulation film formed on the second insulation film, the laminated insulation film having a first opening from which the first pad is exposed; a second coil formed on the laminated insulation film and disposed above the first coil; and a first wiring formed on the laminated insulation film including an upper portion of the first pad exposed from the first opening, the first wiring being electrically connected to the first pad.

公开(公告)号：US09929042B2

公开(公告)日：2018-03-27

申请号：US15150597

申请日：2016-05-10

Applicant: Renesas Electronics Corporation

Inventor： Yoshikazu Tsunemine ,  Takayuki Igarashi

IPC: H01L27/32 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L21/76877 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76847 ,  H01L23/522 ,  H01L23/5222 ,  H01L23/53238 ,  H01L23/53295

Abstract: A semiconductor device, in which an increase in the size of a product can be suppressed and a withstand voltage between wiring layers can be improved, and a manufacturing method thereof are provided. A discontinued part, in which the interface between an interlayer insulating film and a passivation film is discontinued, is formed between a first wiring layer and a second wiring layer that are adjacent to each other with a space therebetween. Both the interlayer insulating film and the passivation film face an air gap in the discontinued part.

公开(公告)号：US09711451B2

公开(公告)日：2017-07-18

申请号：US14418116

申请日：2014-01-29

Applicant: Renesas Electronics Corporation

Inventor： Takayuki Igarashi ,  Takuo Funaya

IPC: H01L27/08 ,  H01L23/522 ,  H01L27/06 ,  H01L27/12 ,  H01L23/00 ,  H01L23/495 ,  H01L23/528 ,  H01L23/532 ,  H01L25/16

CPC classification number: H01L23/5227 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49575 ,  H01L23/5283 ,  H01L23/53214 ,  H01L23/53223 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/167 ,  H01L27/0688 ,  H01L27/1203 ,  H01L2224/02166 ,  H01L2224/05554 ,  H01L2224/45124 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2924/13055 ,  H01L2924/00 ,  H01L2924/00014

Abstract: Characteristics of a semiconductor device are improved. A semiconductor device includes a coil CL1 and a wiring M2 formed on an interlayer insulator IL2, a wiring M3 formed on an interlayer insulator IL3, and a coil CL2 and a wiring M4 formed on the interlayer insulator IL4. Moreover, a distance DM4 between the coil CL2 and the wiring M4 is longer than a distance DM3 between the coil CL2 and the wiring M3 (DM4>DM3). Furthermore, the distance DM3 between the coil CL2 and the wiring M3 is set to be longer than a sum of a film thickness of the interlayer insulator IL3 and a film thickness of the interlayer insulator IL4, which are positioned between the coil CL1 and the coil CL2. In this manner, it is possible to improve an insulation withstand voltage between the coil CL2 and the wiring M4 or the like, where a high voltage difference tend to occur. Moreover, a transformer formation region 1A and a seal ring formation region 1C surrounding a peripheral circuit formation region 1B are formed so as to improve the moisture resistance.