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49 条记录 (耗时 0.022 秒)

    Deposited screen oxide for reducing gate edge lifting
    2.
    发明授权
    Deposited screen oxide for reducing gate edge lifting 有权
    沉积的屏幕氧化物，用于减少门边缘提升

    公开(公告)号：US06518072B1

    公开(公告)日：2003-02-11

    申请号：US09476906

    申请日：2000-01-03

    申请人： Carl Robert Huster ,  Daniel Sobek ,  Timothy Thurgate ,  Sameer S. Haddad

    发明人： Carl Robert Huster ,  Daniel Sobek ,  Timothy Thurgate ,  Sameer S. Haddad

    IPC分类号： H01L218247

    CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42324

    摘要： A method of manufacturing a flash memory device with a controllable amount of gate edge lifting including etching the ends of the tunnel oxide forming a cavity at each end of the tunnel oxide and anisotropically depositing and etching an oxide to form spacers on the sides of the gate stack. The spacers have a predetermined thickness that controls the amount of gate edge lifting. The predetermined thickness is determined during a characterization procedure that can be a computer modeling procedure or it can be determined empirically.

    摘要翻译： 一种制造具有可控量的栅极边缘提升的闪速存储器件的方法，包括蚀刻隧道氧化物的端部，在隧道氧化物的每一端处形成空腔，并各向异性沉积和蚀刻氧化物以在栅极的侧面上形成间隔物 堆栈 间隔物具有控制浇口边缘提升量的预定厚度。 在可以是计算机建模过程的表征过程中确定预定厚度，或者可以凭经验确定。

    Method for inhibiting tunnel oxide growth at the edges of a floating gate during semiconductor device processing
    3.
    发明授权
    Method for inhibiting tunnel oxide growth at the edges of a floating gate during semiconductor device processing 有权
    在半导体器件处理期间抑制浮栅的边缘处的隧道氧化物生长的方法

    公开(公告)号：US06268624B1

    公开(公告)日：2001-07-31

    申请号：US09364982

    申请日：1999-07-31

    申请人： Daniel Sobek ,  Timothy Thurgate ,  Carl R. Huster ,  Tuan Duc Pham ,  Mark T. Ramsbey ,  Sameer S. Haddad

    发明人： Daniel Sobek ,  Timothy Thurgate ,  Carl R. Huster ,  Tuan Duc Pham ,  Mark T. Ramsbey ,  Sameer S. Haddad

    IPC分类号： H01L218247

    CPC分类号： H01L21/28273

    摘要： A method for making a ULSI MOSFET chip includes forming a MOSFET gate stack on a substrate, with a tunnel oxide layer being sandwiched between the gate stack and substrate. To prevent thickening of the tunnel oxide layer into a “gate edge lifting” profile during subsequent oxidation-causing steps, at least one protective barrier film is deposited or grown over the gate stack and tunnel oxide layer immediately after gate stack formation. Then, subsequent steps, including forming source and drain regions for the gate stack, can be undertaken without causing thickening of the tunnel oxide layer.

    摘要翻译： 制造ULSI MOSFET芯片的方法包括在衬底上形成MOSFET栅极叠层，其中隧道氧化层夹在栅叠层和衬底之间。 为了防止隧道氧化物层在随后的氧化引发步骤期间增厚到“栅极边缘提升”轮廓中，在栅极堆叠形成之后立即沉积或生长至少一个保护性阻挡膜在栅极堆叠和隧道氧化物层上。 然后，可以进行包括形成栅极堆叠的源极和漏极区域的后续步骤，而不会导致隧道氧化物层的增厚。

    Method for inhibiting tunnel oxide growth at the edges of a floating gate during semiconductor device processing
    4.
    发明授权
    Method for inhibiting tunnel oxide growth at the edges of a floating gate during semiconductor device processing 有权
    在半导体器件处理期间抑制浮栅的边缘处的隧道氧化物生长的方法

    公开(公告)号：US06337246B1

    公开(公告)日：2002-01-08

    申请号：US09824841

    申请日：2001-04-02

    申请人： Daniel Sobek ,  Timothy Thurgate ,  Carl R. Huster ,  Tuan Duc Pham ,  Mark T. Ramsbey ,  Sameer S. Haddad

    发明人： Daniel Sobek ,  Timothy Thurgate ,  Carl R. Huster ,  Tuan Duc Pham ,  Mark T. Ramsbey ,  Sameer S. Haddad

    IPC分类号： H01L218247

    CPC分类号： H01L21/28273

    摘要： A method for making a ULSI MOSFET chip includes forming a MOSFET gate stack on a substrate, with a tunnel oxide layer being sandwiched between the gate stack and substrate. To prevent thickening of the tunnel oxide layer into a “gate edge lifting” profile during subsequent oxidation-causing steps, at least one protective barrier film is deposited or grown over the gate stack and tunnel oxide layer immediately after gate stack formation. Then, subsequent steps, including forming source and drain regions for the gate stack, can be undertaken without causing thickening of the tunnel oxide layer.

    摘要翻译： 制造ULSI MOSFET芯片的方法包括在衬底上形成MOSFET栅极叠层，其中隧道氧化层夹在栅叠层和衬底之间。 为了防止隧道氧化物层在随后的氧化引发步骤期间增厚到“栅极边缘提升”轮廓中，在栅极堆叠形成之后立即沉积或生长至少一个保护性阻挡膜在栅极堆叠和隧道氧化物层上。 然后，可以进行包括形成栅极堆叠的源极和漏极区域的后续步骤，而不会导致隧道氧化物层的增厚。

    Method of programming a non-volatile memory cell using a current limiter
    5.
    发明授权
    Method of programming a non-volatile memory cell using a current limiter 有权
    使用限流器对非易失性存储单元进行编程的方法

    公开(公告)号：US06269023B1

    公开(公告)日：2001-07-31

    申请号：US09694729

    申请日：2000-10-23

    申请人： Narbeh Derhacobian ,  Janet S. Y. Wang ,  Daniel Sobek ,  Sameer S. Haddad

    发明人： Narbeh Derhacobian ,  Janet S. Y. Wang ,  Daniel Sobek ,  Sameer S. Haddad

    IPC分类号： G11C1604

    CPC分类号： G11C16/10 ,  G11C11/5671 ,  G11C16/0475

    摘要： A memory cell that includes a substrate that has a first region and a second region with a channel therebetween, wherein the first region generates hot carriers. The memory cell further includes a gate above the channel and a charge trapping region that contains a first amount of charge. A current limiter that limits the number of the generated hot carriers that can flow into the channel, wherein the current limiter does not control the voltage of the second region.

    摘要翻译： 一种存储单元，包括具有第一区域的基板和在其间具有通道的第二区域，其中所述第一区域产生热载流子。 存储单元还包括通道上方的栅极和包含第一电荷量的电荷捕获区域。 限流器，其限制可流入通道的所产生的热载体的数量，其中限流器不控制第二区域的电压。

    Biasing method and structure for reducing band-to-band and/or avalanche currents during the erase of flash memory devices
    6.
    发明授权
    Biasing method and structure for reducing band-to-band and/or avalanche currents during the erase of flash memory devices 有权
    在擦除闪速存储器件期间减少带 - 带和/或雪崩电流的偏置方法和结构

    公开(公告)号：US06236596B1

    公开(公告)日：2001-05-22

    申请号：US09461376

    申请日：1999-12-15

    申请人： Daniel Sobek ,  Timothy James Thurgate ,  Scott D. Luning ,  Vei-Han Chan ,  Sameer S. Haddad

    发明人： Daniel Sobek ,  Timothy James Thurgate ,  Scott D. Luning ,  Vei-Han Chan ,  Sameer S. Haddad

    IPC分类号： G11C1134

    CPC分类号： G11C16/14

    摘要： A method and apparatus for reducing band-to-band currents during the erasure of a flash EEPROM memory cell is provided. The apparatus has a back biasing connection on the substrate at which a biasing voltage is applied during erasure of the flash EEPROM memory cell. The method of applying the biasing voltage to the back biasing connection during erasure of the flash EEPROM memory cell reduces band-to-band current between the source region and the substrate during erasure of the flash memory cell. This reduction provides for gate size reduction in flash memory cells without inducing detrimental short channel effects.

    摘要翻译： 提供了一种用于在快速EEPROM存储单元的擦除期间减小带 - 带电流的方法和装置。 该装置在衬底上具有背偏压连接，在擦除EEPROM存储单元期间施加偏置电压。 在闪存EEPROM存储单元擦除期间将偏置电压施加到反向偏置连接的方法在擦除闪速存储单元期间减少源区和衬底之间的带间电流。 这种减少提供了闪存单元的栅极尺寸减小，而不会引起有害的短沟道效应。

    Microfluidic Liquid Stream Configuration System
    8.
    发明申请
    Microfluidic Liquid Stream Configuration System 有权
    微流体液流配置系统

    公开(公告)号：US20080251383A1

    公开(公告)日：2008-10-16

    申请号：US12064630

    申请日：2006-08-23

    申请人： Daniel Sobek ,  Jun Zeng

    发明人： Daniel Sobek ,  Jun Zeng

    IPC分类号： G01N27/00

    CPC分类号： B01L3/502792 ,  B01L3/50273 ,  B01L3/502738 ,  B01L2300/0645 ,  B01L2300/069 ,  B01L2300/089 ,  B01L2400/0415 ,  B01L2400/0448 ,  B01L2400/06 ,  F04B19/006 ,  G01N33/4905

    摘要： A microfluidic liquid stream configuration system is provided including providing a substrate; forming a first co-planar electrode and a second co-planar electrode on the substrate; applying a dielectric layer, with a controlled surface energy, on the first co-planar electrode and the second co-planar electrode; forming an input reservoir on the first co-planar electrode and a second co-planar electrode; supplying a liquid in the input reservoir for analysis; and imposing an electric field, an electric field gradient, or a combination thereof on the liquid for respectively driving surface charge or dipole moments in the liquid for configuring a liquid stream.

    摘要翻译： 提供了一种微流体液流配置系统，包括提供基板; 在所述基板上形成第一共面电极和第二共面电极; 在所述第一共平面电极和所述第二共面电极上施加具有受控表面能的电介质层; 在所述第一共平面电极和第二共面电极上形成输入容器; 在输入容器中供应液体进行分析; 并在液体上施加电场，电场梯度或其组合，以分别驱动用于构成液体流的液体中的表面电荷或偶极矩。