公开(公告)号：US06268289B1

公开(公告)日：2001-07-31

申请号：US09080809

申请日：1998-05-18

申请人： Rina Chowdhury ,  Ajay Jain ,  Olubunmi Adetutu

发明人： Rina Chowdhury ,  Ajay Jain ,  Olubunmi Adetutu

IPC分类号： H01L2144

CPC分类号： H01L21/76874 ,  H01L21/2885 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76861 ,  H01L21/76865 ,  H01L21/76873 ,  H01L21/76879 ,  H01L2221/1089

摘要： A method for forming a copper interconnect begins by depositing a barrier layer (48) within an in-laid region (18). An edge exclusion protection layer (50) is formed over the barrier layer (48), and this layer (50) is processed so that it only lies within the edge exclusion region (20) of the wafer. The layer (50) is removed from active area portions of the wafer so that contact resistance of copper interconnects is not affected. Wet surface processing is used to form a catalyst (64b) on the wafer surface to enable electroless copper plating within active areas of the wafer to form a copper seed layer (52). The layer (52) is not formed in an edge exclusion region (20). Electroplating is then used to thicken the copper material to form a copper layer (54) over the layer (52) wherein the in-laid copper interconnect is completed.

摘要翻译： 用于形成铜互连的方法通过在屏蔽区域（18）内沉积阻挡层（48）开始。 边缘排除保护层（50）形成在阻挡层（48）上方，并且该层（50）被处理，使得其仅位于晶片的边缘排除区域（20）内。 从晶片的有效区域部分去除层（50），使得铜互连的接触电阻不受影响。 使用湿表面处理在晶片表面上形成催化剂（64b），以在晶片的有效区域内实现化学镀铜以形成铜籽晶层（52）。 层（52）不形成在边缘排除区域（20）中。 然后使用电镀来增厚铜材料，以在其上完成嵌入式铜互连的层（52）上形成铜层（54）。

公开(公告)号：US06429531B1

公开(公告)日：2002-08-06

申请号：US09551312

申请日：2000-04-18

申请人： Addi B. Mistry ,  Rina Chowdhury ,  Scott K. Pozder ,  Deborah A. Hagen ,  Rebecca G. Cole ,  Kartik Ananthanarayanan ,  George F. Carney

发明人： Addi B. Mistry ,  Rina Chowdhury ,  Scott K. Pozder ,  Deborah A. Hagen ,  Rebecca G. Cole ,  Kartik Ananthanarayanan ,  George F. Carney

IPC分类号： H01L2348

CPC分类号： H01L24/11 ,  H01L23/3171 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05567 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11472 ,  H01L2224/119 ,  H01L2224/11912 ,  H01L2224/13022 ,  H01L2224/13076 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/83101 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01009 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/01083 ,  H01L2924/00012 ,  H01L2924/013

摘要： An interconnect structure, such as a flip-chip structure, including a base pad and a stud formed on the base pad and extending from the base pad is disclosed. The stud and base pad are formed to be continuous and of substantially the same electrically conductive base material. Typically, a solder structure is formed on the stud wherein the solder structure is exposed for subsequent reflow attachment to another structure. The present invention relates to packaging integrated circuits, more particularly to the structure and processing of a stud and bump without the standard under bump metallurgy.

摘要翻译： 公开了一种互连结构，例如倒装芯片结构，包括形成在基座上并从基座延伸的基座和螺柱。 螺柱和基垫形成为连续的和基本上相同的导电基材。 通常，焊料结构形成在螺柱上，其中焊料结构被暴露以用于随后的回流附接到另一结构。 本发明涉及封装集成电路，更具体地涉及没有标准凸块下冶金的螺柱和凸块的结构和加工。

公开(公告)号：US06297155B1

公开(公告)日：2001-10-02

申请号：US09305093

申请日：1999-05-03

申请人： Cindy Reidsema Simpson ,  Robert Douglas Mikkola ,  Matthew T. Herrick ,  Brett Caroline Baker ,  David Moralez Pena ,  Edward Acosta ,  Rina Chowdhury ,  Marijean Azrak ,  Cindy Kay Goldberg ,  Mohammed Rabiul Islam

发明人： Cindy Reidsema Simpson ,  Robert Douglas Mikkola ,  Matthew T. Herrick ,  Brett Caroline Baker ,  David Moralez Pena ,  Edward Acosta ,  Rina Chowdhury ,  Marijean Azrak ,  Cindy Kay Goldberg ,  Mohammed Rabiul Islam

IPC分类号： H01L2144

CPC分类号： H01L21/76877 ,  H01L21/2885

摘要： A method for electroplating a copper layer (118) over a wafer (20) powers a cathode of an electroplating system (10) in a manner that obtains improved copper interconnects. A control system (34) powers the cathode of the system (10) with a mix of two or more of: (i) positive low-powered DC cycles (201 or 254); (ii) positive high-powered DC cycles (256 or 310); (iii) low-powered, pulsed, positive-power cycles (306 or 530); (iv) high-powered, pulsed, positive-powered cycles (212, 252, 302, or 352); and/or (v) negative pulsed cycles (214, 304, 510, 528, or 532). The collection of these cycles functions to electroplate copper or a like metal (118) onto the wafer (20). During electroplating, insitu process control and/or endpointing (506, 512, or 520) is performed to further improve the resulting copper interconnect.

摘要翻译： 在晶片（20）上电镀铜层（118）的方法以获得改进的铜互连的方式为电镀系统（10）的阴极供电。 控制系统（34）以下列两种或多种的混合来为系统（10）的阴极供电：（i）正低功率DC循环（201或254）; （ii）正极大功率直流循环（256或310）; （iii）低功率，脉冲，正功率周期（306或530）; （iv）高功率，脉冲，正动​​力循环（212,252,302或352）; 和/或（v）负脉冲循环（214,304,510,528或532）。 这些循环的收集用于将铜或类似金属（118）电镀到晶片（20）上。 在电镀期间，执行基底过程控制和/或终点（506,512或520）以进一步改善所得铜互连。