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1.发明授权Method of fabricating an embedded polysilicon resistor and an embedded eFuse isolated from a substrate 有权制造嵌入式多晶硅电阻器和从基板隔离的嵌入式eFuse的方法公开(公告)号：US08377790B2
公开(公告)日：2013-02-19
申请号：US13014995
申请日：2011-01-27
IPC分类号： H01L21/20
CPC分类号： H01L28/20 , H01L21/76224 , H01L23/5256 , H01L27/0629 , H01L2924/0002 , H01L2924/00
摘要： A method includes providing a substrate having insulating layers thereon; forming a first trench in a first region of the substrate and a second trench in a second region of the substrate; thermally growing layers of oxide along the sides of the trenches; filling the first trench and the second trench with a polysilicon material, planarizing the polysilicon material, and creating a shallow trench isolation between the first region and the second region, wherein the step f) of creating the shallow trench isolation is performed only after the steps of d) filling and e) planarizing.
摘要翻译： 一种方法包括提供其上具有绝缘层的基板; 在所述衬底的第一区域中形成第一沟槽和在所述衬底的第二区域中形成第二沟槽; 沿着沟槽的侧面的氧化物的热生长层; 用多晶硅材料填充第一沟槽和第二沟槽，平坦化多晶硅材料，以及在第一区域和第二区域之间产生浅沟槽隔离，其中仅在步骤之后才执行产生浅沟槽隔离的步骤f） 的d）填充和e）平面化。
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2.发明申请METHOD OF FABRICATION BODIES FOR AN EMBEDDED POLYSILICON RESISTOR AND AN EMBEDDED eFUSE ISOLATED FROM A SUBSTRATE 有权嵌入式多晶硅电阻的制造方法和从基板分离的嵌入式电解液公开(公告)号：US20120196423A1
公开(公告)日：2012-08-02
申请号：US13014995
申请日：2011-01-27
IPC分类号： H01L21/762 , H01L21/02 , H01L21/768
CPC分类号： H01L28/20 , H01L21/76224 , H01L23/5256 , H01L27/0629 , H01L2924/0002 , H01L2924/00
摘要： A method includes providing a substrate having insulating layers thereon; forming a first trench in a first region of the substrate and a second trench in a second region of the substrate; thermally growing layers of oxide along the sides of the trenches; filling the first trench and the second trench with a polysilicon material, planarizing the polysilicon material, and creating a shallow trench isolation between the first region and the second region, wherein the step f) of creating the shallow trench isolation is performed only after the steps of d) filling and e) planarizing.
摘要翻译： 一种方法包括提供其上具有绝缘层的基板; 在所述衬底的第一区域中形成第一沟槽和在所述衬底的第二区域中形成第二沟槽; 沿着沟槽的侧面的氧化物的热生长层; 用多晶硅材料填充第一沟槽和第二沟槽，平坦化多晶硅材料，以及在第一区域和第二区域之间产生浅沟槽隔离，其中仅在步骤之后才执行产生浅沟槽隔离的步骤f） 的d）填充和e）平面化。
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公开(公告)号：US08410559B2
公开(公告)日：2013-04-02
申请号：US12407007
申请日：2009-03-19
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/517 , H01L21/02126 , H01L21/02211 , H01L21/02282 , H01L21/28123 , H01L21/3105 , H01L21/3121 , H01L21/76224 , H01L29/495 , H01L29/4966 , H01L29/518
摘要： A shallow trench isolation structure is formed in a semiconductor substrate adjacent to an active semiconductor region. A selective self-assembling oxygen barrier layer is formed on the surface of the shallow trench isolation structure that includes a dielectric oxide material. The formation of the selective self-assembling oxygen barrier layer is selective in that it is not formed on the surface the active semiconductor region having a semiconductor surface. The selective self-assembling oxygen barrier layer is a self-assembled monomer layer of a chemical which is a derivative of alkylsilanes including at least one alkylene moiety. The silicon containing portion of the chemical forms polysiloxane, which is bonded to surface silanol groups via Si—O—Si bonds. The monolayer of the chemical is the selective self-assembling oxygen barrier layer that prevents diffusion of oxygen to a high dielectric constant material layer that is subsequently deposited as a gate dielectric.
摘要翻译： 在与有源半导体区域相邻的半导体衬底中形成浅沟槽隔离结构。 在包括电介质氧化物材料的浅沟槽隔离结构的表面上形成选择性自组装氧阻挡层。 选择性自组装氧阻挡层的形成是选择性的，因为它不在具有半导体表面的有源半导体区域的表面上形成。 选择性自组装氧阻挡层是化学品的自组装单体层，其是包括至少一个亚烷基部分的烷基硅烷的衍生物。 化学式的含硅部分形成聚硅氧烷，其通过Si-O-Si键与表面硅烷醇基团键合。 化学品的单层是选择性自组装氧阻挡层，其防止氧扩散到随后沉积为栅极电介质的高介电常数材料层。
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4.发明申请TWO STEP METHOD TO CREATE A GATE ELECTRODE USING A PHYSICAL VAPOR DEPOSITED LAYER AND A CHEMICAL VAPOR DEPOSITED LAYER 审中-公开使用物理蒸气沉积层和化学气相沉积层创建门电极的两步法公开(公告)号：US20100155860A1
公开(公告)日：2010-06-24
申请号：US12344046
申请日：2008-12-24
IPC分类号： H01L29/43 , H01L21/283 , H01L21/336 , C23C14/34
CPC分类号： H01L21/28088 , H01L21/28079 , H01L21/823842 , H01L29/495 , H01L29/4966 , H01L29/66545
摘要： One embodiment of the present invention relates a semiconductor device formed by utilizing a two step deposition method for forming a gate electrode without causing damages to an underlying gate dielectric material. In one embodiment, a first layer of gate electrode material (first gate electrode layer) is formed onto the surface of a gate dielectric material using a deposition that does not damage the gate dielectric material (e.g., physical vapor deposition) thereby resulting in a damage free interface between the gate dielectric material and the gate electrode material. A second layer of gate electrode material (second gate electrode layer) is then formed onto the first layer of gate electrode material using a chemical deposition method that provides increased deposition control (e.g., good layer uniformity, impurity control, etc.). The first and second gate electrode layers are then selectively patterned to cumulatively form a semiconductor device's gate electrode.
摘要翻译： 本发明的一个实施例涉及通过利用用于形成栅电极的两步沉积方法形成的半导体器件，而不会对下面的栅介质材料造成损害。 在一个实施例中，使用不损坏栅极电介质材料（例如，物理气相沉积）的沉积，在栅极电介质材料的表面上形成第一层栅电极材料（第一栅电极层），从而导致损坏 栅介电材料和栅电极材料之间的自由界面。 然后使用提供增加的沉积控制（例如，良好的层均匀性，杂质控制等）的化学沉积方法将第二层栅电极材料（第二栅极电极层）形成在第一层栅电极材料层上。 然后，第一和第二栅极电极层被选择性地图案化以累积地形成半导体器件的栅电极。
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公开(公告)号：US20090170258A1
公开(公告)日：2009-07-02
申请号：US11965024
申请日：2007-12-27
IPC分类号： H01L21/8238 , H01L21/28
CPC分类号： H01L21/823835 , H01L21/28097 , H01L21/823864 , H01L29/4975 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： One embodiment relates to a method of fabricating an integrated circuit. In the method, p-type polysilicon is provided over a semiconductor body, where the p-type polysilicon has a first depth as measured from a top surface of the p-type polysilicon. An n-type dopant is implanted into the p-type polysilicon to form a counter-doped layer at the top-surface of the p-type polysilicon, where the counter-doped layer has a second depth that is less than the first depth. A catalyst metal is provided that associates with the counter-doped layer to form a catalytic surface. A metal is deposited over the catalytic surface. A thermal process is performed that reacts the metal with the p-type polysilicon in the presence of the catalytic surface to form a metal silicide. Other methods and devices are also disclosed.
摘要翻译： 一个实施例涉及一种制造集成电路的方法。 在该方法中，p型多晶硅设置在半导体本体上，其中p型多晶硅具有从p型多晶硅的顶表面测量的第一深度。 将n型掺杂剂注入到p型多晶硅中以在p型多晶硅的顶表面上形成反掺杂层，其中反掺杂层具有小于第一深度的第二深度。 提供催化剂金属，其与反掺杂层相结合以形成催化剂表面。 金属沉积在催化剂表面上。 进行热处理，其在催化剂表面存在下使金属与p型多晶硅反应形成金属硅化物。 还公开了其它方法和装置。
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公开(公告)号：US20090032877A1
公开(公告)日：2009-02-05
申请号：US11832037
申请日：2007-08-01
申请人： Mark R. Visokay , Shaofeng Yu
发明人： Mark R. Visokay , Shaofeng Yu
IPC分类号： H01L21/8236 , H01L29/78
CPC分类号： H01L21/823864 , H01L21/823807 , H01L29/7847
摘要： A method of manufacturing a semiconductor device includes forming transistors including gate electrodes and source/drain regions over a substrate. A protective layer is placed over the source/drain regions and the gate electrodes. A portion of the protective layer is removed to expose a portion of the gate electrodes. The exposed portions of the gate electrodes are amorphized, and remaining portions of the protective layer located over the source/drain regions are removed. A stress memorization layer is formed over the gate electrodes, and the substrate is annealed in the presence of the stress memorization layer to at least reduce an amorphous content of the gate electrodes. The stress memorization layer is removed subsequent to the annealing.
摘要翻译： 制造半导体器件的方法包括在衬底上形成包括栅电极和源/漏区的晶体管。 保护层放置在源极/漏极区域和栅极电极之上。 去除保护层的一部分以露出栅电极的一部分。 栅电极的露出部分是非晶化的，并且去除位于源极/漏极区上方的保护层的剩余部分。 在栅电极上形成应力记忆层，并且在应力存储层的存在下对基板进行退火，以至少降低栅电极的无定形含量。 在退火之后去除应力记忆层。
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公开(公告)号：US07351626B2
公开(公告)日：2008-04-01
申请号：US10739617
申请日：2003-12-18
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L21/02318 , C23C16/56 , H01L21/02323 , H01L21/28185 , H01L21/28194 , H01L21/3143 , H01L21/31608 , H01L21/31616 , H01L21/31641 , H01L21/31645 , H01L21/318 , H01L29/518 , H01L29/78
摘要： A method for improving high-κ gate dielectric film (104) properties. The high-κ film (104) is subjected to a two step anneal sequence. The first anneal is performed in a reducing ambient (106) with low partial pressure of oxidizer to promote film relaxation and increase by-product diffusion and desorption. The second anneal is performed in an oxidizing ambient (108) with a low partial pressure of reducer to remove defects and impurities.
摘要翻译： 一种改善高卡门电介质膜（104）性能的方法。 对高卡帕膜（104）进行两步退火处理。 第一退火在具有低分压氧化剂的还原环境（106）中进行，以促进膜弛豫并增加副产物扩散和解吸附。 第二次退火在具有低分压还原剂的氧化环境（108）中进行以除去缺陷和杂质。
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公开(公告)号：US07253049B2
公开(公告)日：2007-08-07
申请号：US11017469
申请日：2004-12-20
申请人： Jiong-Ping Lu , Shaofeng Yu , Haowen Bu , Lindsey H. Hall , Mark R. Visokay
发明人： Jiong-Ping Lu , Shaofeng Yu , Haowen Bu , Lindsey H. Hall , Mark R. Visokay
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842 , H01L21/28097 , H01L21/28518 , H01L29/4975 , H01L29/51 , H01L29/6659 , H01L29/7833
摘要： A method for making PMOS and NMOS transistors 60, 70 on a semiconductor substrate 20 that includes having a gate protection layer 210 over the gate electrode layer 110 during the formation of source/drain silicides 120. The method may include implanting dopants into a gate polysilicon layer 115 before forming the protection layer 215.
摘要翻译： 一种用于在半导体衬底20上制造PMOS和NMOS晶体管60,70的方法，其包括在源/漏硅化物120形成期间在栅电极层110上方具有栅极保护层210。 该方法可以包括在形成保护层215之前将掺杂剂注入到栅极多晶硅层115中。
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9.发明授权High-k gate dielectric with uniform nitrogen profile and methods for making the same 有权具有均匀氮分布的高k栅极电介质及其制造方法公开(公告)号：US06809370B1
公开(公告)日：2004-10-26
申请号：US10632230
申请日：2003-07-31
申请人： Luigi Colombo , Manuel Quevedo-Lopez , James J. Chambers , Mark R. Visokay , Antonio L. P. Rotondaro
发明人： Luigi Colombo , Manuel Quevedo-Lopez , James J. Chambers , Mark R. Visokay , Antonio L. P. Rotondaro
IPC分类号： H01L27108
CPC分类号： H01L29/518 , H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L29/6659 , H01L29/7833
摘要： High-k transistor gate structures and fabrication methods therefor are provided, wherein a gate dielectric interface region near a semiconductor substrate is provided with very little or no nitrogen, while the bulk high-k dielectric is provided with a uniform nitrogen concentration.
摘要翻译： 提供了高k晶体管栅极结构及其制造方法，其中在半导体衬底附近的栅极电介质界面区域设置有非常少的或不具有氮的，而本体高k电介质具有均匀的氮浓度。
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10.发明授权Methods of depositing a layer comprising tungsten and methods of forming a transistor gate line 有权沉积包含钨的层的方法和形成晶体管栅极线的方法公开(公告)号：US06617250B2
公开(公告)日：2003-09-09
申请号：US10243406
申请日：2002-09-13
IPC分类号： H01L21302
CPC分类号： H01L21/31122 , H01L21/28061 , H01L21/28518 , H01L21/28556 , H01L21/28568 , H01L21/31604 , H01L21/32051 , H01L27/10811 , H01L27/10888 , H01L28/90 , H01L29/6659
摘要： In part, disclosed are semiconductor processing methods, methods of depositing a tungsten comprising layer over a substrate, methods of depositing a tungsten nitride comprising layer over a substrate, methods of depositing a tungsten silicide comprising layer over a substrate, methods of forming a transistor gate line over a substrate, methods of forming a patterned substantially crystalline Ta2O5 comprising material, and methods of forming a capacitor dielectric region comprising substantially crystalline Ta2O5 comprising material. In one implementation, a semiconductor processing method includes forming a substantially amorphous Ta2O5 comprising layer over a semiconductive substrate. The layer is exposed to WF6 under conditions effective to etch substantially amorphous Ta2O5 from the substrate. In one implementation, the layer is exposed to WF6 under conditions effective to both etch substantially amorphous Ta2O5 from the substrate and deposit a tungsten comprising layer over the substrate during the exposing.
摘要翻译： 部分地，公开了半导体处理方法，在衬底上沉积含钨层的方法，在衬底上沉积含氮化钨的层的方法，在衬底上沉积包含硅化钨的层的方法，形成晶体管栅极的方法 在衬底上划线，形成图案化的基本上结晶的Ta 2 O 5的材料的方法，以及形成包含基本上结晶的Ta 2 O 5的材料的电容器电介质区域的方法。 在一个实施方案中，半导体处理方法包括在半导体衬底上形成包含基本非晶态的Ta 2 O 5层。 该层在有效从底物上蚀刻基本无定形Ta 2 O 5的条件下暴露于WF6。 在一个实施方案中，该层在有效地从衬底上蚀刻基本上无定形Ta 2 O 5的条件下暴露于WF6，并在曝光期间在衬底上沉积含钨层。
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