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公开(公告)号：US06384642B1
公开(公告)日：2002-05-07
申请号：US09680572
申请日：2000-10-06
申请人： Robert J. Bosnyak , José M. Cruz , Robert J. Drost
发明人： Robert J. Bosnyak , José M. Cruz , Robert J. Drost
IPC分类号： H03B100
CPC分类号： H04L25/0292 , H04L25/0278
摘要： In an input receiver circuit includes a signal input for receiving a signal input to a chip, a chip output for supplying a buffered signal to circuitry on the chip and a positive feedback circuit coupled between the chip output and the signal input. The positive feedback circuit might comprise a first inverter having an input coupled to the signal input, a second inverter having an input coupled to an output of the first inverter, wherein an output of the second inverter provides the chip output, and an inverting buffer having an input coupled to the output of the second inverter and an output coupled to the signal input.
摘要翻译： 在输入接收机电路中包括用于接收输入到芯片的信号的信号输入端，用于将缓冲信号提供给芯片上的电路的芯片输出端以及耦合在芯片输出和信号输入端之间的正反馈电路。 正反馈电路可以包括具有耦合到信号输入的输入的第一反相器，具有耦合到第一反相器的输出的输入的第二反相器，其中第二反相器的输出提供芯片输出，反相缓冲器具有 耦合到第二反相器的输出的输入端和耦合到信号输入的输出。
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公开(公告)号：US06597593B1
公开(公告)日：2003-07-22
申请号：US09614664
申请日：2000-07-12
申请人： José M. Cruz , Robert J. Bosnyak , Shwetabh Verma
发明人： José M. Cruz , Robert J. Bosnyak , Shwetabh Verma
IPC分类号： H02M100
CPC分类号： H01L27/08 , G06F1/26 , H01F17/0006 , H01F19/04 , H01F27/2804 , H02M7/003
摘要： A power converter within an integrated circuit (“IC”) for providing DC power to one or more function circuit, where the power converter has a transformer circuit for receiving an AC power signal and for supplying a transformed AC power signal. A converter circuit receives the transformed AC power signal and then converts the signal into a DC power signal supplied to one or more function circuit. The transformed AC power signal might either be stepped up or stepped down. The transformer circuit might comprise two coils, where a first coil is magnetically coupled to a second coil. The first coil is a first spiral and the second coil is a second spiral wherein an insulating material layer is disposed between the first spiral and the second spiral. The transformer circuit might include transformers connected in parallel or in series and may further be connected correspondingly to more than one converter circuit coupled in parallel. An IC comprising the power converter circuit can be integrated into a computer system.
摘要翻译： 用于向一个或多个功能电路提供直流电力的集成电路（“IC”）内的功率转换器，其中功率转换器具有用于接收AC电力信号的变压器电路并用于提供经变换的AC电力信号。 A转换器电路接收经变换的AC电力信号，然后将该信号转换为提供给一个或多个功能电路的直流电力信号。 变换后的交流电源信号可能会升高或降低。 变压器电路可以包括两个线圈，其中第一线圈磁耦合到第二线圈。 第一线圈是第一螺旋，第二线圈是第二螺旋形，其中绝缘材料层设置在第一螺旋和第二螺旋之间。 变压器电路可以包括并联或串联连接的变压器，并且可以进一步相应地连接到并联耦合的多于一个的转换器电路。 包括电源转换器电路的IC可以集成到计算机系统中。
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3.发明授权公开(公告)号：US06362678B1
公开(公告)日：2002-03-26
申请号：US09468710
申请日：1999-12-21
申请人： Robert J. Bosnyak , José M. Cruz
发明人： Robert J. Bosnyak , José M. Cruz
IPC分类号： H03K1704
CPC分类号： H03K19/0136 , H03K19/01728
摘要： An improved output driver for HSTL includes a bias control transistor to absorb current leaking through the base-collector capacitance of the drive transistor and maintain the base voltage on the drive transistor. The bias control transistor is biased by a series network coupled between a base of the bias control transistor and ground, which keeps the bias control transistor at a bias near its turn-on bias, with a feedback capacitor coupled between the output and the base of the bias control transistor to turn on the bias control transistor when the output rises.
摘要翻译： 用于HSTL的改进的输出驱动器包括偏置控制晶体管，以吸收通过驱动晶体管的基极 - 集电极电容泄漏的电流并且维持驱动晶体管上的基极电压。 偏置控制晶体管被耦合在偏置控制晶体管的基极和接地之间的串联网络偏置，该偏置控制晶体管的基极与接地之间保持偏置控制晶体管的偏压，反馈电容器耦合在输出和基极之间 偏置控制晶体管，当输出上升时导通偏置控制晶体管。
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公开(公告)号：US06738415B2
公开(公告)日：2004-05-18
申请号：US09815358
申请日：2001-03-22
申请人： Robert J. Drost , Robert J. Bosnyak
发明人： Robert J. Drost , Robert J. Bosnyak
IPC分类号： H04B138
CPC分类号： H04L5/14 , H04L25/085 , H04L27/367
摘要： A bi-directional communication system and transceiver configuration are described, which employ a bi-directional reference to account for both common-mode and differential noise introduced at either end of a bi-directional communication channel. Some implementations exploit the techniques described in a bi-directional chip-to-chip communication scheme. In some implementations, the advantages of bi-directional reference techniques described herein are obtained while pre-distortion of transmitted signals is employed to compensate for intersymbol interference (ISI) in a communications channel.
摘要翻译： 描述了双向通信系统和收发器配置，其采用双向参考来考虑在双向通信信道的任一端引入的共模和差分噪声。 一些实现利用了双向芯片到芯片通信方案中描述的技术。 在一些实现中，本文所述的双向参考技术的优点是获得的，同时采用发射信号的预失真来补偿通信信道中的符号间干扰（ISI）。
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公开(公告)号：US6031406A
公开(公告)日：2000-02-29
申请号：US883524
申请日：1997-06-26
申请人： Robert J. Drost , Robert J. Bosnyak , Jose M. Cruz
发明人： Robert J. Drost , Robert J. Bosnyak , Jose M. Cruz
CPC分类号： H01L27/0207
摘要： An apparatus for suppressing the effect of noise from a first circuit on the performance of a second circuit wherein the first and second circuits are on a common substrate. Each of the first and second circuits include first and second supply rails. The apparatus includes a noise isolation circuit and a noise transference circuit. The noise isolation circuit is for coupling the first supply rails of the first and second circuits to prevent noise on the first supply rail of the first circuit from transferring to the first supply rail of the second circuit. The noise transference circuit is for coupling the second supply rails of the first and second circuits so that noise on the second supply rail of the first circuit is transferred to the second supply rail of the second circuit.
摘要翻译： 一种用于抑制来自第一电路的噪声对第二电路的性能的影响的装置，其中第一和第二电路在公共衬底上。 第一和第二电路中的每一个包括第一和第二电源轨。 该装置包括噪声隔离电路和噪声转移电路。 噪声隔离电路用于耦合第一和第二电路的第一电源轨，以防止第一电路的第一电源轨上的噪声转移到第二电路的第一电源轨。 噪声转移电路用于耦合第一和第二电路的第二电源轨，使得第一电路的第二电源轨上的噪声被传送到第二电路的第二电源轨。
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公开(公告)号：US5982834A
公开(公告)日：1999-11-09
申请号：US854151
申请日：1997-05-09
申请人： Robert J. Drost , Robert J. Bosnyak
发明人： Robert J. Drost , Robert J. Bosnyak
CPC分类号： H03L7/0995 , H03L7/24 , H04L7/033 , H03L7/083
摘要： A clock recovery system that allows recovery of a clock signal from a high speed, potentially small amplitude data stream. The invention uses a normally avoided property of a non-linear oscillator in the clock recovery system in order to lock the oscillator in phase to an incoming signal. This property relates a characteristic of an oscillator that an oscillator amplifies noise near its inherent frequency; and if the noise is large enough, the oscillator squelches the inherent oscillator frequency signal and outputs a signal locked in frequency and phase to the noise. The clock recovery system comprises a processing circuit, an oscillator, and a control circuit. The processing circuit processes an input data stream to generate a current signal as a first control signal based on data transitions in the input data stream. The first control signal is a "noise signal" to the oscillator. The control circuit outputs a voltage control signal as a second signal to the oscillator based on a difference between an output fed back from the oscillator and a reference frequency signal matching the frequency of the input data stream within a predetermined tolerance range. The second control signal controls the oscillator so that the frequency of the oscillator output is substantially equal to that of the input data stream. Therefore, according to the invention, the oscillator is controlled by the first control signal such that the oscillator output is phase-locked and thus also frequency-locked to the input data stream.
摘要翻译： 时钟恢复系统，允许从高速，潜在的小幅度数据流恢复时钟信号。 本发明在时钟恢复系统中使用非线性振荡器的正常避免的特性，以将振荡器锁相到输入信号。 该属性涉及振荡器的特征，振荡器放大其固有频率附近的噪声; 并且如果噪声足够大，则振荡器对固有的振荡器频率信号进行静噪，并输出锁定在频率和相位上的噪声信号。 时钟恢复系统包括处理电路，振荡器和控制电路。 处理电路基于输入数据流中的数据转换来处理输入数据流以产生作为第一控制信号的当前信号。 第一控制信号是振荡器的“噪声信号”。 控制电路基于从振荡器反馈的输出与在预定公差范围内与输入数据流的频率匹配的参考频率信号之间的差异，向振荡器输出电压控制信号作为第二信号。 第二控制信号控制振荡器，使得振荡器输出的频率基本上等于输入数据流的频率。 因此，根据本发明，振荡器由第一控制信号控制，使得振荡器输出被锁相，因此也被频率锁定到输入数据流。
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公开(公告)号：US06987412B2
公开(公告)日：2006-01-17
申请号：US10816761
申请日：2004-04-02
CPC分类号： H03K5/003 , H01L23/48 , H01L25/0657 , H01L2225/06527 , H01L2924/00013 , H01L2924/0002 , H03K3/037 , H03K17/689 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2924/00
摘要： A system is presented for latching and amplifying a capacitively coupled inter-chip communication signal that operates by receiving an input signal on a capacitive receiver pad and feeding the input signal through an inverter to produce an output signal. The output signal is fed back through a weakened inverter to produce a feedback signal that is fed into an input of the inverter to form a latch for the input signal. The weakened inverter is biased to produce a feedback signal that swings between a high bias voltage, VH, and a low bias voltage, VL. VH is set slightly higher than the switching threshold of the inverter, and VL is set slightly lower than the switching threshold. This feedback signal causes the input signal to reside within a narrow voltage range near the switching threshold of the inverter, thereby making the inverter sensitive to small transitions in the input signal.
摘要翻译： 提出了一种用于锁存和放大电容耦合的芯片间通信信号的系统，其通过接收电容性接收器焊盘上的输入信号并通过反相器馈送输入信号以产生输出信号来操作。 输出信号通过弱化逆变器反馈，产生反馈信号，该反馈信号馈送到反相器的输入端，形成输入信号的锁存器。 弱化的逆变器被偏置以产生在高偏置电压V H H和低偏压V L之间摆动的反馈信号。 V H设定得比逆变器的切换阈值略高，并且将V L L设定得比切换阈值略低。 该反馈信号使得输入信号驻留在接近逆变器的开关阈值的窄电压范围内，从而使得反相器对输入信号中的小转变敏感。
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公开(公告)号：US06696876B2
公开(公告)日：2004-02-24
申请号：US09759981
申请日：2001-01-12
申请人： Robert J. Drost , Robert J. Bosnyak
发明人： Robert J. Drost , Robert J. Bosnyak
IPC分类号： H03K300
摘要： A clock interpolation circuit for setting and controlling a phase of an output clock that is derived from an interpolation of multiple input clocks. Interpolation is performed by capacitively weighting the multiple clocks. A select and control circuit provides the ability to select different capacitance values to control the weighting. An optional buffer stage is also provided to sharpen the edge transitions of the interpolated clock.
摘要翻译： 一种用于设置和控制从多个输入时钟的内插导出的输出时钟的相位的时钟插值电路。 通过对多个时钟进行电容加权来执行插值。 选择和控制电路提供选择不同电容值以控制加权的能力。 还提供了可选的缓冲级，以锐化内插时钟的边沿转换。
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9.发明授权
公开(公告)号：US06148038A
公开(公告)日：2000-11-14
申请号：US828506
申请日：1997-03-31
申请人： Robert J. Drost , Robert J. Bosnyak
发明人： Robert J. Drost , Robert J. Bosnyak
CPC分类号： H04L25/4904 , H03H5/12
摘要： A decoder circuit for decoding phase-encoded digital data signals includes a timing circuit and a signal viewer circuit coupled to logic circuitry. The timing circuit uses an edge of a received phase-encoded digital data signal to indicate when to sample data from the received phase-encoded digital data signal in the signal viewer circuit. The logic circuitry determines the value encoded in the phase-encoded digital data signal based on the sampled data.
摘要翻译： 用于解码相位编码的数字数据信号的解码器电路包括定时电路和耦合到逻辑电路的信号查看器电路。 定时电路使用接收的相位编码数字数据信号的边沿来指示何时在信号查看器电路中从接收到的相位编码的数字数据信号中采样数据。 逻辑电路基于采样数据确定编码在相位编码数字数据信号中的值。
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10.发明授权Phase error cancellation method and apparatus for high performance data recovery 失效用于高性能数据恢复的相位误差消除方法和装置
公开(公告)号：US5963606A
公开(公告)日：1999-10-05
申请号：US884052
申请日：1997-06-27
申请人： Robert J. Drost , Robert J. Bosnyak
发明人： Robert J. Drost , Robert J. Bosnyak
CPC分类号： H03L7/0805 , H03L7/07 , H03L7/0812 , H03L7/0995 , H04L7/0037 , H04L7/0337 , H04L7/0041
摘要： A phase error cancellation apparatus captures data bits of a serialized data stream with reduced phase error by aligning a generated clock signal to the data stream. The phase error cancellation apparatus includes a data delay pipe, a clock generator, a clock delay pipe, and a data stream sampling element. The data delay pipe receives the data stream and delays the data bits by a first amount. The clock generator generates a clock signal that the clock delay pipe delays by a second amount. The data stream sampling element receives the delayed data bits and the delayed clock signal, and samples the delayed data bits using the delayed clock signal to recover the data bits from the data stream with reduced phase error.
摘要翻译： 相位误差消除装置通过将生成的时钟信号与数据流对齐来捕获具有减小的相位误差的串行化数据流的数据位。 相位误差消除装置包括数据延迟管，时钟发生器，时钟延迟管和数据流采样元件。 数据延迟管接收数据流并将数据位延迟第一个量。 时钟发生器产生时钟延迟管延迟第二个量的时钟信号。 数据流采样单元接收延迟的数据位和延迟的时钟信号，并使用延迟的时钟信号对延迟的数据位进行采样，以从相位误差减小的数据流中恢复数据位。
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