利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

115 条记录 (耗时 0.03 秒)

    Data processing device with memory coupling unit
    1.
    发明授权
    Data processing device with memory coupling unit 有权
    具有存储器耦合单元的数据处理设备

    公开(公告)号：US06405273B1

    公开(公告)日：2002-06-11

    申请号：US09192170

    申请日：1998-11-13

    申请人： Rod G. Fleck ,  Klaus Oberlaender ,  Gigy Baror ,  Alfred Eder ,  Le Trong Nguyen

    发明人： Rod G. Fleck ,  Klaus Oberlaender ,  Gigy Baror ,  Alfred Eder ,  Le Trong Nguyen

    IPC分类号： G06F1300

    CPC分类号： G06F13/1678

    摘要： A data processing unit is disclosed with a register file having a plurality of registers. A memory having a plurality of n-bit input/output ports, and a coupling unit for coupling the memory with the register file, a memory address and select unit for addressing the memory banks are provided. The coupling unit comprises a bus having a bus width of at least 2n-bits forming at least a first and second sub-bus, first couplers for coupling each memory bank or the register file selectively with one of the sub-busses, and second couplers for coupling the register file or the memory banks with the bus.

    摘要翻译： 公开了具有多个寄存器的寄存器文件的数据处理单元。 提供具有多个n位输入/输出端口的存储器，以及用于将存储器与寄存器文件耦合的耦合单元，用于寻址存储体的存储器地址和选择单元。 耦合单元包括具有形成至少第一和第二子总线的至少2n位的总线宽度的总线，用于将每个存储体或寄存器文件选择性地耦合到子总线之一的第一耦合器和第二耦合器 用于将寄存器文件或存储体与总线耦合。

    Streamlined instruction processor
    3.
    发明授权
    Streamlined instruction processor 失效
    精简指令处理器

    公开(公告)号：US4926323A

    公开(公告)日：1990-05-15

    申请号：US163917

    申请日：1988-03-03

    申请人： Gigy Baror ,  Brian W. Case ,  Rod G. Fleck ,  Philip M. Freidin ,  Smeeta Gupta ,  William M. Johnson ,  Cheng-Gang Kong ,  Ole H. Moller ,  Timothy A. Olson ,  David I. Sorensen

    发明人： Gigy Baror ,  Brian W. Case ,  Rod G. Fleck ,  Philip M. Freidin ,  Smeeta Gupta ,  William M. Johnson ,  Cheng-Gang Kong ,  Ole H. Moller ,  Timothy A. Olson ,  David I. Sorensen

    IPC分类号： G06F9/38

    CPC分类号： G06F9/3804 ,  G06F9/3867

    摘要： A streamlined instruction processor processes data in response to a program composed of prespecified instructions in pipeline cycles. The processor comprises an instruction fetch unit, including an instruction interface adapted for connection to an instruction memory and for fetching instructions from the instruction memory. The instruction fetch unit includes an instruction prefetch buffer coupled to the instruction interface for buffering a sequence of instructions supplied to the instruction interface. A branch target cache is coupled with the prefetch buffer for storing sets of instructions retrieved from a corresponding set of locations in the instruction memory, having sequential instruction addresses. The first instruction in each such set is a branch target instruction in the program.In addition, an execution unit including a data interface adapted for connection to the data memory, executes the instructions in pipeline cycles. The execution unit includes a storage facility, coupled to the data interface, for storing data in a file of data locations identified by file addresses. The storage facility includes at least two read ports and one write port operable in response to file addresses. An addressing unit coupled to receive the instructions from the instruction register, supplies the file addresses to the read ports and the write port under program control. In addition, the addressing unit is operable in response to a stack pointer providing dynamic allocation of the file of data locations to processes within the program.A memory management unit is coupled to the data interface. The memory management unit includes an address interface adapted for connection to the data memory and the instruction memory for supplying instruction addresses to the instruction memory and data addresses to the data memory, in a simple single access mode, a pipeline mode and a burst mode.

    摘要翻译： 精简指令处理器响应于由流水线循环中的预先指定组成的程序来处理数据。 处理器包括指令提取单元，其包括适于连接到指令存储器并用于从指令存储器取出指令的指令接口。 指令提取单元包括指令预取缓冲器，其耦合到指令接口，用于缓冲提供给指令接口的指令序列。 分支目标高速缓冲存储器与预取缓冲器耦合，用于存储从指令存储器中的对应的一组位置检索的具有顺序指令地址的指令集。 每个这样的集合中的第一条指令是程序中的分支目标指令。 此外，包括适于连接到数据存储器的数据接口的执行单元在流水线循环中执行指令。 执行单元包括耦合到数据接口的存储设备，用于将数据存储在由文件地址标识的数据位置的文件中。 存储设备包括至少两个读端口和一个可响应文件地址操作的写端口。 耦合以从指令寄存器接收指令的寻址单元，在程序控制下将文件地址提供给读端口和写端口。 此外，寻址单元响应于堆栈指针提供动态分配数据位置文件到程序内的进程而可操作。 存储器管理单元耦合到数据接口。 存储器管理单元包括适于连接到数据存储器的地址接口和用于以简单的单次访问模式，流水线模式和突发模式向指令存储器提供指令地址和数据存储器的指令存储器。

    Memory device with support for unaligned access
    4.
    发明授权
    Memory device with support for unaligned access 有权
    支持未对齐访问的内存设备

    公开(公告)号：US06512716B2

    公开(公告)日：2003-01-28

    申请号：US09772497

    申请日：2001-01-29

    申请人： Klaus Oberlaender ,  Sabeen Randhawa ,  Vincent Rez{haeck over (a)}rd ,  Rod G. Fleck

    发明人： Klaus Oberlaender ,  Sabeen Randhawa ,  Vincent Rez{haeck over (a)}rd ,  Rod G. Fleck

    IPC分类号： G11C700

    CPC分类号： G11C7/1006 ,  G11C8/10 ,  G11C8/12

    摘要： An integrated memory comprises a plurality of data lines and a plurality of decoders being associated to each data line. Each data line can address a single memory cell or a plurality of memory cells. Also, each data line can be either a word line or a bit line of a memory. Each decoder generates an enable signal upon receiving of its associated address signal. A plurality of multiplexers having two inputs and an output associated to each data line are provided. The enable signal of each decoder is supplied to a first input of the associated multiplexer and to a second input of the multiplexer associated to the next higher addressed data line, and a control input for controlling said multiplexers.

    摘要翻译： 集成存储器包括多个数据线和与每个数据线相关联的多个解码器。 每个数据线可以寻址单个存储器单元或多个存储器单元。 此外，每个数据线可以是存储器的字线或位线。 每个解码器在接收到其相关联的地址信号时产生使能信号。 提供具有两个输入和与每条数据线相关联的输出的多路复用器。 每个解码器的使能信号被提供给相关联的多路复用器的第一输入和与下一较高寻址数据线相关联的复用器的第二输入，以及用于控制所述多路复用器的控制输入。

    Memory device with support for unaligned access
    5.
    发明授权
    Memory device with support for unaligned access 有权
    支持未对齐访问的内存设备

    公开(公告)号：US06256253B1

    公开(公告)日：2001-07-03

    申请号：US09507568

    申请日：2000-02-18

    申请人： Klaus Oberlaender ,  Sabeen Randhawa ,  Vincent Rez{haeck over (a)}rd ,  Rod G. Fleck

    发明人： Klaus Oberlaender ,  Sabeen Randhawa ,  Vincent Rez{haeck over (a)}rd ,  Rod G. Fleck

    IPC分类号： G11C700

    CPC分类号： G11C7/1006 ,  G11C8/10 ,  G11C8/12

    摘要： An integrated memory comprises a plurality of data lines and a plurality of decoders being associated to each data line. Each data line can address a single memory cell or a plurality of memory cells. Also, each data line can be either a word line or a bit line of a memory. Each decoder generates an enable signal upon receiving of its associated address signal. A plurality of multiplexers having two inputs and an output associated to each data line are provided. The enable signal of each decoder is supplied to a first input of the associated multiplexer and to a second input of the multiplexer associated to the next higher addressed data line, and a control input for controlling said multiplexers.

    摘要翻译： 集成存储器包括多个数据线和与每个数据线相关联的多个解码器。 每个数据线可以寻址单个存储器单元或多个存储器单元。 此外，每个数据线可以是存储器的字线或位线。 每个解码器在接收到其相关联的地址信号时产生使能信号。 提供具有两个输入和与每条数据线相关联的输出的多路复用器。 每个解码器的使能信号被提供给相关联的多路复用器的第一输入和与下一较高寻址数据线相关联的复用器的第二输入，以及用于控制所述多路复用器的控制输入。

    SELECTIVE OCCLUSION SYSTEM FOR AUGMENTED REALITY DEVICES
    7.
    发明申请
    SELECTIVE OCCLUSION SYSTEM FOR AUGMENTED REALITY DEVICES 审中-公开
    选择性的现场设备选择性系统

    公开(公告)号：US20160247319A1

    公开(公告)日：2016-08-25

    申请号：US14628099

    申请日：2015-02-20

    申请人： Andreas G. Nowatzyk ,  Joel Pritchett ,  Rod G. Fleck

    发明人： Andreas G. Nowatzyk ,  Joel Pritchett ,  Rod G. Fleck

    IPC分类号： G06T19/00 ,  G06T15/50 ,  G02B27/01 ,  G02F1/1335

    CPC分类号： G06T19/006 ,  G02B27/017 ,  G02B27/0172 ,  G02B2027/0138 ,  G02B2027/0141 ,  G02B2027/0178 ,  G02B2027/0187 ,  G02F1/133528 ,  G06F3/011 ,  G06T15/50

    摘要： Examples are disclosed that relate to selectively dimming or occluding light from a real-world background to enhance the display of virtual objects on a near-eye display. One example provides a near-eye display system including a see-through display, an image source, a background light sensor, a selective background occluder comprising a first liquid crystal panel and a second liquid crystal panel positioned between a pair of polarizers, and a computing device including instructions executable by a logic subsystem to determine a shape and a position of an occlusion area based upon a virtual object to be displayed, obtain a first and a second birefringence pattern for the first and the second liquid crystal panels, produce the occlusion area by applying the birefringence patterns to the liquid crystal panels, and display the virtual object in a location visually overlapping with the occlusion area.

    摘要翻译： 公开了涉及从真实世界背景中选择性地调光或遮挡光以增强近眼显示器上的虚拟物体的显示的实例。 一个例子提供了一种近眼显示系统，包括透视显示器，图像源，背景光传感器，包括位于一对偏振器之间的第一液晶面板和第二液晶面板的选择性背景遮蔽器，以及 计算装置，包括可由逻辑子系统执行的指令，以基于要显示的虚拟对象来确定遮挡区域的形状和位置，获得第一和第二液晶面板的第一和第二双折射图案，产生遮挡 通过将双折射图案应用于液晶面板，并将虚拟物体显示在与遮挡区域视觉重叠的位置。

    AUDIO FOCUSING VIA MULTIPLE MICROPHONES
    10.
    发明申请
    AUDIO FOCUSING VIA MULTIPLE MICROPHONES 有权
    音频聚焦通过多个麦克风

    公开(公告)号：US20150054943A1

    公开(公告)日：2015-02-26

    申请号：US13972781

    申请日：2013-08-21

    申请人： Syavosh Zad Issa ,  Rod G. Fleck

    发明人： Syavosh Zad Issa ,  Rod G. Fleck

    IPC分类号： H04N7/18 ,  H04R29/00 ,  H04R3/00

    CPC分类号： H04N7/18 ,  H04R3/005 ,  H04R29/004 ,  H04R2410/01 ,  H04R2460/07 ,  H04R2499/11 ,  H04R2499/15

    摘要： Various technologies are applied to focus audio received from a plurality of microphones of a mobile device. A camera can be used to portray a scene, and a selection within the scene can focus audio to a desired audio focus region. Techniques can account for movement of the mobile device or an object being tracked. Pre-computed audio filters can be used to customize the audio focus process to account for a particular mobile device geometry.

    摘要翻译： 应用各种技术来聚焦从移动设备的多个麦克风接收的音频。 相机可用于描绘场景，并且场景内的选择可将音频聚焦到所需的音频对焦区域。 技术可以解释移动设备或被跟踪对象的移动。 预先计算的音频滤波器可用于定制音频聚焦过程以考虑特定的移动设备几何。