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    Temperature stable metal nitride gate electrode
    2.
    发明授权
    Temperature stable metal nitride gate electrode 有权
    温度稳定的金属氮化物栅电极

    公开(公告)号：US07023064B2

    公开(公告)日：2006-04-04

    申请号：US10710063

    申请日：2004-06-16

    申请人： Dae-Gyu Park ,  Cyril Cabral, Jr. ,  Oleg Gluschenkov ,  Hyungjun Kim

    发明人： Dae-Gyu Park ,  Cyril Cabral, Jr. ,  Oleg Gluschenkov ,  Hyungjun Kim

    IPC分类号： H01L29/76

    CPC分类号： H01L21/823842 ,  H01L21/823857 ,  Y10S257/90 ,  Y10S438/942

    摘要： An integrated circuit is provided including an FET gate structure formed on a substrate. This structure includes a gate dielectric on the substrate, and a metal nitride layer overlying the gate dielectric and in contact therewith. This metal nitride layer is characterized as MNx, where M is one of W, Re, Zr, and Hf, and x is in the range of about 0.7 to about 1.5. Preferably the layer is of WNx, and x is about 0.9. Varying the nitrogen concentration in the nitride layer permits integration of different FET characteristics on the same chip. In particular, varying x in the WNx layer permits adjustment of the threshold voltage in the different FETs. The polysilicon depletion effect is substantially reduced, and the gate structure can be made thermally stable up to about 1000° C.

    摘要翻译： 提供了一种集成电路，其包括形成在衬底上的FET栅极结构。 该结构包括衬底上的栅极电介质和覆盖栅极电介质并与其接触的金属氮化物层。 该金属氮化物层的特征在于MN x，其中M是W，Re，Zr和Hf之一，x在约0.7至约1.5的范围内。 优选地，该层为W N x X，x为约0.9。 改变氮化物层中的氮浓度允许在同一芯片上集成不同的FET特性。 特别地，在WN 层中改变x允许调节不同FET中的阈值电压。 多晶硅耗尽效应显着降低，并且栅极结构可以在高达约1000℃下热稳定。

    Temperature stable metal nitride gate electrode
    3.
    发明授权
    Temperature stable metal nitride gate electrode 有权
    温度稳定的金属氮化物栅电极

    公开(公告)号：US07282403B2

    公开(公告)日：2007-10-16

    申请号：US11203952

    申请日：2005-08-15

    申请人： Dae-Gyu Park ,  Cyril Cabral, Jr. ,  Oleg Gluschenkov ,  Hyungjun Kim

    发明人： Dae-Gyu Park ,  Cyril Cabral, Jr. ,  Oleg Gluschenkov ,  Hyungjun Kim

    IPC分类号： H01L21/8238 ,  H01L21/3205 ,  H01L21/4763

    CPC分类号： H01L21/823842 ,  H01L21/823857 ,  Y10S257/90 ,  Y10S438/942

    摘要： An integrated circuit is provided including an FET gate structure formed on a substrate. This structure includes a gate dielectric on the substrate, and a metal nitride layer overlying the gate dielectric and in contact therewith. This metal nitride layer is characterized as MNx, where M is one of W, Re, Zr, and Hf, and x is in the range of about 0.7 to about 1.5. Preferably the layer is of WNx, and x is about 0.9. Varying the nitrogen concentration in the nitride layer permits integration of different FET characteristics on the same chip. In particular, varying x in the WNx layer permits adjustment of the threshold voltage in the different FETs. The polysilicon depletion effect is substantially reduced, and the gate structure can be made thermally stable up to about 1000° C.

    摘要翻译： 提供了一种集成电路，其包括形成在衬底上的FET栅极结构。 该结构包括衬底上的栅极电介质和覆盖栅极电介质并与其接触的金属氮化物层。 该金属氮化物层的特征在于MN x，其中M是W，Re，Zr和Hf之一，x在约0.7至约1.5的范围内。 优选地，该层为W N x X，x为约0.9。 改变氮化物层中的氮浓度允许在同一芯片上集成不同的FET特性。 特别地，在WN 层中改变x允许调节不同FET中的阈值电压。 多晶硅耗尽效应显着降低，并且栅极结构可以在高达约1000℃下热稳定。

    High performance FET with laterally thin extension
    4.
    发明授权
    High performance FET with laterally thin extension 失效
    高性能FET，横向薄延伸

    公开(公告)号：US07176116B2

    公开(公告)日：2007-02-13

    申请号：US11074223

    申请日：2005-03-07

    申请人： Cyril Cabral, Jr. ,  Omer H. Dokumaci ,  Oleg Gluschenkov

    发明人： Cyril Cabral, Jr. ,  Omer H. Dokumaci ,  Oleg Gluschenkov

    IPC分类号： H01L21/3205 ,  H01L21/4763 ,  H01L21/31 ,  H01L21/469

    CPC分类号： H01L21/28194 ,  H01L21/28202 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7836

    摘要： A field effect transistor (FET), integrated circuit (IC) chip including the FETs and a method of forming the FETs. The FETs have a device channel and a gate above the device channel with a doped source/drain extension at said each end of the thin channel. A portion of a low resistance material layer (e.g., a silicide layer) is disposed on source/drain extensions. The portions on the doped extensions laterally form a direct contact with the doped source/drain extension. Any low resistance material layer on the gate is separated from the low resistance material portions on the source/drain extensions.

    摘要翻译： 包括FET的场效应晶体管（FET），集成电路（IC）芯片和形成FET的方法。 FET在器件沟道上方具有器件沟道和栅极，在薄沟道的每个端部具有掺杂的源极/漏极延伸。 低电阻材料层（例如硅化物层）的一部分设置在源极/漏极延伸部分上。 掺杂延伸部分上的部分横向形成与掺杂源极/漏极延伸部的直接接触。 栅极上的任何低电阻材料层与源极/漏极延伸部分上的低电阻材料部分分离。

    Temperature stable metal nitride gate electrode
    6.
    发明申请
    Temperature stable metal nitride gate electrode 有权

    公开(公告)号：US20060040439A1

    公开(公告)日：2006-02-23

    申请号：US11203952

    申请日：2005-08-15

    申请人： Dae-Gyu Park ,  Cyril Cabral ,  Oleg Gluschenkov ,  Hyungjun Kim

    发明人： Dae-Gyu Park ,  Cyril Cabral ,  Oleg Gluschenkov ,  Hyungjun Kim

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823842 ,  H01L21/823857 ,  Y10S257/90 ,  Y10S438/942

    摘要： An integrated circuit is provided including an FET gate structure formed on a substrate. This structure includes a gate dielectric on the substrate, and a metal nitride layer overlying the gate dielectric and in contact therewith. This metal nitride layer is characterized as MNx, where M is one of W, Re, Zr, and Hf, and x is in the range of about 0.7 to about 1.5. Preferably the layer is of WNx, and x is about 0.9. Varying the nitrogen concentration in the nitride layer permits integration of different FET characteristics on the same chip. In particular, varying x in the WNx layer permits adjustment of the threshold voltage in the different FETs. The polysilicon depletion effect is substantially reduced, and the gate structure can be made thermally stable up to about 1000° C.

    TEMPERATURE STABLE METAL NITRIDE GATE ELECTRODE
    7.
    发明申请
    TEMPERATURE STABLE METAL NITRIDE GATE ELECTRODE 有权
    温度稳定的金属硝酸盐电极

    公开(公告)号：US20050280099A1

    公开(公告)日：2005-12-22

    申请号：US10710063

    申请日：2004-06-16

    申请人： Dae-Gyu Park ,  Cyril Cabral ,  Oleg Gluschenkov ,  Hyungjun Kim

    发明人： Dae-Gyu Park ,  Cyril Cabral ,  Oleg Gluschenkov ,  Hyungjun Kim

    IPC分类号： H01L21/8238 ,  H01L29/76

    CPC分类号： H01L21/823842 ,  H01L21/823857 ,  Y10S257/90 ,  Y10S438/942

    摘要： An integrated circuit is provided including an FET gate structure formed on a substrate. This structure includes a gate dielectric on the substrate, and a metal nitride layer overlying the gate dielectric and in contact therewith. This metal nitride layer is characterized as MNx, where M is one of W, Re, Zr, and Hf, and x is in the range of about 0.7 to about 1.5. Preferably the layer is of WNx, and x is about 0.9. Varying the nitrogen concentration in the nitride layer permits integration of different FET characteristics on the same chip. In particular, varying x in the WNx layer permits adjustment of the threshold voltage in the different FETs. The polysilicon depletion effect is substantially reduced, and the gate structure can be made thermally stable up to about 1000° C.

    摘要翻译： 提供了一种集成电路，其包括形成在衬底上的FET栅极结构。 该结构包括衬底上的栅极电介质和覆盖栅极电介质并与其接触的金属氮化物层。 该金属氮化物层的特征在于MN x，其中M是W，Re，Zr和Hf之一，x在约0.7至约1.5的范围内。 优选地，该层为W N x X，x为约0.9。 改变氮化物层中的氮浓度允许在同一芯片上集成不同的FET特性。 特别地，在WN 层中改变x允许调节不同FET中的阈值电压。 多晶硅耗尽效应显着降低，并且栅极结构可以在高达约1000℃下热稳定。

    ULTRA-THIN SILICIDATION-STOP EXTENSIONS IN MOSFET DEVICES
    10.
    发明申请
    ULTRA-THIN SILICIDATION-STOP EXTENSIONS IN MOSFET DEVICES 有权

    公开(公告)号：US20050112857A1

    公开(公告)日：2005-05-26

    申请号：US10707175

    申请日：2003-11-25

    申请人： Oleg Gluschenkov ,  Cyril Cabral ,  Omer Dokumaci ,  Christian Lavoie

    发明人： Oleg Gluschenkov ,  Cyril Cabral ,  Omer Dokumaci ,  Christian Lavoie

    IPC分类号： H01L21/285 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/08 ,  H01L29/78

    CPC分类号： H01L29/0847 ,  H01L21/28518 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7833

    摘要： Very low resistance, scaled in MOSFET devices are formed by employing thin silicidation-stop extension that act both as a silicidation “stop” barriers and as thin interface layers between source/drain silicide regions and channel region of the MOSFET. By acting as silicidation stops, the silicidation-stop extensions confine silicidation, and are not breached by source/drain silicide. This permits extremely thin, highly-doped silicidation-stop extensions to be formed between the silicide and the channel, providing an essentially ideal, low series resistance interface between the silicide an the channel. On an appropriately prepared substrate, a selective etching process is performed to expose the sides of the channel region (transistor body). A very thin layer of a silicidation-stop material, e.g., SiGe, is disposed in the etched away area, coating the exposed sides of the channel region. The silicidation-stop material is doped (highly) appropriately for the type of MOSFET being formed (n-channel or p-channel). The etched away areas are then filled with silicon, e.g., by an Si epi process. Silicidation is then performed (to form, e.g., CoSi2) on the newly filled areas. The silicidation stop material constrains silicidation to the silicon fill material, but prevents silicide expansion past the silicidation stop material. Because the germanium (Ge) in SiGe is insoluble in CoSi2, the SiGe acts as a barrier to silicidation, permitting silicidation to go to completion in the Si fill but stopping silicidation at the SiGe boundary when silicidation is performed at a temperature above a silicidation threshold temperature for Si, but below a silicidation threshold temperature for SiGe. This results in a very compact, well-defined lateral junction characterized by a thin layer of SiGe disposed between silicide lateral extensions and the sides of the channel region. Because of the thin, highly-doped SiGe layer between the channel and the silicide lateral extensions, the extension resistance is very low.