利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

62 条记录 (耗时 0.026 秒)

    ULTRA-THIN SILICIDATION-STOP EXTENSIONS IN MOSFET DEVICES
    3.
    发明申请
    ULTRA-THIN SILICIDATION-STOP EXTENSIONS IN MOSFET DEVICES 有权

    公开(公告)号：US20050112857A1

    公开(公告)日：2005-05-26

    申请号：US10707175

    申请日：2003-11-25

    申请人： Oleg Gluschenkov ,  Cyril Cabral ,  Omer Dokumaci ,  Christian Lavoie

    发明人： Oleg Gluschenkov ,  Cyril Cabral ,  Omer Dokumaci ,  Christian Lavoie

    IPC分类号： H01L21/285 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/08 ,  H01L29/78

    CPC分类号： H01L29/0847 ,  H01L21/28518 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7833

    摘要： Very low resistance, scaled in MOSFET devices are formed by employing thin silicidation-stop extension that act both as a silicidation “stop” barriers and as thin interface layers between source/drain silicide regions and channel region of the MOSFET. By acting as silicidation stops, the silicidation-stop extensions confine silicidation, and are not breached by source/drain silicide. This permits extremely thin, highly-doped silicidation-stop extensions to be formed between the silicide and the channel, providing an essentially ideal, low series resistance interface between the silicide an the channel. On an appropriately prepared substrate, a selective etching process is performed to expose the sides of the channel region (transistor body). A very thin layer of a silicidation-stop material, e.g., SiGe, is disposed in the etched away area, coating the exposed sides of the channel region. The silicidation-stop material is doped (highly) appropriately for the type of MOSFET being formed (n-channel or p-channel). The etched away areas are then filled with silicon, e.g., by an Si epi process. Silicidation is then performed (to form, e.g., CoSi2) on the newly filled areas. The silicidation stop material constrains silicidation to the silicon fill material, but prevents silicide expansion past the silicidation stop material. Because the germanium (Ge) in SiGe is insoluble in CoSi2, the SiGe acts as a barrier to silicidation, permitting silicidation to go to completion in the Si fill but stopping silicidation at the SiGe boundary when silicidation is performed at a temperature above a silicidation threshold temperature for Si, but below a silicidation threshold temperature for SiGe. This results in a very compact, well-defined lateral junction characterized by a thin layer of SiGe disposed between silicide lateral extensions and the sides of the channel region. Because of the thin, highly-doped SiGe layer between the channel and the silicide lateral extensions, the extension resistance is very low.

    Temperature stable metal nitride gate electrode
    4.
    发明申请
    Temperature stable metal nitride gate electrode 有权

    公开(公告)号：US20060040439A1

    公开(公告)日：2006-02-23

    申请号：US11203952

    申请日：2005-08-15

    申请人： Dae-Gyu Park ,  Cyril Cabral ,  Oleg Gluschenkov ,  Hyungjun Kim

    发明人： Dae-Gyu Park ,  Cyril Cabral ,  Oleg Gluschenkov ,  Hyungjun Kim

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823842 ,  H01L21/823857 ,  Y10S257/90 ,  Y10S438/942

    摘要： An integrated circuit is provided including an FET gate structure formed on a substrate. This structure includes a gate dielectric on the substrate, and a metal nitride layer overlying the gate dielectric and in contact therewith. This metal nitride layer is characterized as MNx, where M is one of W, Re, Zr, and Hf, and x is in the range of about 0.7 to about 1.5. Preferably the layer is of WNx, and x is about 0.9. Varying the nitrogen concentration in the nitride layer permits integration of different FET characteristics on the same chip. In particular, varying x in the WNx layer permits adjustment of the threshold voltage in the different FETs. The polysilicon depletion effect is substantially reduced, and the gate structure can be made thermally stable up to about 1000° C.

    TEMPERATURE STABLE METAL NITRIDE GATE ELECTRODE
    6.
    发明申请
    TEMPERATURE STABLE METAL NITRIDE GATE ELECTRODE 有权
    温度稳定的金属硝酸盐电极

    公开(公告)号：US20050280099A1

    公开(公告)日：2005-12-22

    申请号：US10710063

    申请日：2004-06-16

    申请人： Dae-Gyu Park ,  Cyril Cabral ,  Oleg Gluschenkov ,  Hyungjun Kim

    发明人： Dae-Gyu Park ,  Cyril Cabral ,  Oleg Gluschenkov ,  Hyungjun Kim

    IPC分类号： H01L21/8238 ,  H01L29/76

    CPC分类号： H01L21/823842 ,  H01L21/823857 ,  Y10S257/90 ,  Y10S438/942

    摘要： An integrated circuit is provided including an FET gate structure formed on a substrate. This structure includes a gate dielectric on the substrate, and a metal nitride layer overlying the gate dielectric and in contact therewith. This metal nitride layer is characterized as MNx, where M is one of W, Re, Zr, and Hf, and x is in the range of about 0.7 to about 1.5. Preferably the layer is of WNx, and x is about 0.9. Varying the nitrogen concentration in the nitride layer permits integration of different FET characteristics on the same chip. In particular, varying x in the WNx layer permits adjustment of the threshold voltage in the different FETs. The polysilicon depletion effect is substantially reduced, and the gate structure can be made thermally stable up to about 1000° C.

    摘要翻译： 提供了一种集成电路，其包括形成在衬底上的FET栅极结构。 该结构包括衬底上的栅极电介质和覆盖栅极电介质并与其接触的金属氮化物层。 该金属氮化物层的特征在于MN x，其中M是W，Re，Zr和Hf之一，x在约0.7至约1.5的范围内。 优选地，该层为W N x X，x为约0.9。 改变氮化物层中的氮浓度允许在同一芯片上集成不同的FET特性。 特别地，在WN 层中改变x允许调节不同FET中的阈值电压。 多晶硅耗尽效应显着降低，并且栅极结构可以在高达约1000℃下热稳定。

    Method and process for forming a self-aligned silicide contact
    10.
    发明申请
    Method and process for forming a self-aligned silicide contact 有权
    用于形成自对准硅化物接触的方法和工艺

    公开(公告)号：US20060051961A1

    公开(公告)日：2006-03-09

    申请号：US10935497

    申请日：2004-09-07

    申请人： Cyril Cabral ,  Michael Cobb ,  Balasubramanian Pranatharthi Haran ,  Randolph Knarr ,  Mahadevaiyer Krishnan ,  Christian Lavoie ,  Andrew Mansson ,  Horatio Wildman

    发明人： Cyril Cabral ,  Michael Cobb ,  Balasubramanian Pranatharthi Haran ,  Randolph Knarr ,  Mahadevaiyer Krishnan ,  Christian Lavoie ,  Andrew Mansson ,  Horatio Wildman

    IPC分类号： H01L21/44

    CPC分类号： H01L21/28518 ,  H01L21/28052 ,  H01L29/665

    摘要： The present invention provides a method for forming a self-aligned Ni alloy silicide contact. The method of the present invention begins by first depositing a conductive Ni alloy with Pt and optionally at least one of the following metals Pd, Rh, Ti, V, Cr, Zr, Nb, Mo, Hf, Ta, W or Re over an entire semiconductor structure which includes at least one gate stack region. An oxygen diffusion barrier comprising, for example, Ti, TiN or W is deposited over the structure to prevent oxidation of the metals. An annealing step is then employed to cause formation of a NiSi, PtSi contact in regions in which the metals are in contact with silicon. The metal that is in direct contact with insulating material such as SiO2 and Si3N4 is not converted into a metal alloy silicide contact during the annealing step. A selective etching step is then performed to remove unreacted metal from the sidewalls of the spacers and trench isolation regions.

    摘要翻译： 本发明提供一种形成自对准Ni合金硅化物接触的方法。 本发明的方法首先首先用Pt和任选的以下金属Pd，Rh，Ti，V，Cr，Zr，Nb，Mo，Hf，Ta，W或Re中的至少一种沉积导电Ni合金， 整个半导体结构，其包括至少一个栅极堆叠区域。 包含例如Ti，TiN或W的氧扩散阻挡层沉积在结构上以防止金属的氧化。 然后使用退火步骤在金属与硅接触的区域中形成NiSi，PtSi接触。 与诸如SiO 2和Si 3 N 4 N之类的绝缘材料直接接触的金属在金属合金硅化物接触期间不会转化为金属合金硅化物接触 退火步骤。 然后执行选择性蚀刻步骤以从间隔物和沟槽隔离区域的侧壁去除未反应的金属。