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    Methods of Forming Replacement Gate Structures for Semiconductor Devices
    1.
    发明申请
    Methods of Forming Replacement Gate Structures for Semiconductor Devices 审中-公开
    形成半导体器件的替代栅极结构的方法

    公开(公告)号：US20130187236A1

    公开(公告)日：2013-07-25

    申请号：US13354844

    申请日：2012-01-20

    申请人： Ruilong Xie ,  Xiuyu Cai ,  Robert Miller ,  Andreas Knorr

    发明人： Ruilong Xie ,  Xiuyu Cai ,  Robert Miller ,  Andreas Knorr

    IPC分类号： H01L27/092 ,  H01L21/28

    CPC分类号： H01L29/4966 ,  H01L21/82345 ,  H01L21/823456 ,  H01L21/823842 ,  H01L21/82385 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553

    摘要： Disclosed herein are methods of forming replacement gate structures. In one example, the method includes forming a sacrificial gate structure above a semiconducting substrate, removing the sacrificial gate structure to thereby define a gate cavity, forming a layer of insulating material in the gate cavity and forming a layer of metal within the gate cavity above the layer of insulating material. The method further includes forming a sacrificial material in the gate cavity so as to cover a portion of the layer of metal and thereby define an exposed portion of the layer of metal, performing an etching process on the exposed portion of the layer of metal to thereby remove the exposed portion of the layer of metal from within the gate cavity, and, after performing the etching process, removing the sacrificial material and forming a conductive material above the remaining portion of the layer of metal.

    摘要翻译： 这里公开了形成替换栅极结构的方法。 在一个示例中，该方法包括在半导体衬底之上形成牺牲栅极结构，去除牺牲栅极结构从而限定栅极腔，在栅极腔中形成绝缘材料层并在栅极腔内形成金属层 绝缘材料层。 该方法还包括在栅腔中形成牺牲材料以覆盖金属层的一部分，从而限定金属层的暴露部分，对金属层的暴露部分进行蚀刻工艺，由此 从栅极腔内去除金属层的暴露部分，并且在执行蚀刻工艺之后，去除牺牲材料并在金属层的剩余部分上方形成导电材料。

    Semiconductor structures and methods for forming isolation between Fin structures of FinFET devices
    3.
    发明授权
    Semiconductor structures and methods for forming isolation between Fin structures of FinFET devices 有权
    用于在FinFET器件的Fin结构之间形成隔离的半导体结构和方法

    公开(公告)号：US09257325B2

    公开(公告)日：2016-02-09

    申请号：US12562849

    申请日：2009-09-18

    申请人： Andreas Knorr ,  Frank Scott Johnson

    发明人： Andreas Knorr ,  Frank Scott Johnson

    IPC分类号： H01L29/06 ,  H01L21/762 ,  H01L29/66 ,  H01L29/78

    CPC分类号： H01L21/76229 ,  H01L29/66795 ,  H01L29/7851

    摘要： Semiconductor structures and methods for forming isolation between fin structures formed from a bulk silicon wafer are provided. A bulk silicon wafer is provided having one or more fin structures formed therefrom. Forming of the fin structures defines isolation trenches between the one or more fin structures. Each of the fin structures has vertical sidewalls. An oxide layer is deposited in the isolation trenches and on the vertical sidewalls using HDPCVD in about a 4:1 ratio or greater. The oxide layer is isotropically etched to remove the oxide layer from the vertical sidewalls and a portion of the oxide layer from the bottom of the isolation trenches. A substantially uniformly thick isolating oxide layer is formed on the bottom of the isolation trench to isolate the one or more fin structures and substantially reduce fin height variability.

    摘要翻译： 提供了用于形成由体硅晶片形成的翅片结构之间的隔离的半导体结构和方法。 提供具有由其形成的一个或多个翅片结构的体硅晶片。 翅片结构的形成限定了一个或多个翅片结构之间的隔离沟槽。 每个翅片结构都具有垂直侧壁。 使用HDPCVD以大约4:1的比例或更大的比例在隔离沟槽和垂直侧壁上沉积氧化物层。 氧化层被各向同性蚀刻以从隔离沟底部的垂直侧壁和氧化物层的一部分去除氧化物层。 在隔离沟槽的底部上形成基本上均匀的厚的隔离氧化物层，以隔离一个或多个翅片结构，并显着降低翅片高度的可变性。

    METHOD FOR SELF-ALIGNING A STOP LAYER TO A REPLACEMENT GATE FOR SELF-ALIGNED CONTACT INTEGRATION
    8.
    发明申请
    METHOD FOR SELF-ALIGNING A STOP LAYER TO A REPLACEMENT GATE FOR SELF-ALIGNED CONTACT INTEGRATION 有权
    将自动对准停止层的方法用于自对准接触集成的替换门

    公开(公告)号：US20110062501A1

    公开(公告)日：2011-03-17

    申请号：US12561708

    申请日：2009-09-17

    申请人： Steven R. Soss ,  Andreas Knorr

    发明人： Steven R. Soss ,  Andreas Knorr

    IPC分类号： H01L29/78 ,  H01L21/28

    CPC分类号： H01L29/4966 ,  H01L21/28114 ,  H01L21/76834 ,  H01L21/76895 ,  H01L21/76897 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656 ,  Y10S438/926

    摘要： Semiconductor devices with replacement gate electrodes and integrated self aligned contacts are formed with enhanced gate dielectric layers and improved electrical isolation properties between the gate line and a contact. Embodiments include forming a removable gate electrode on a substrate, forming a self aligned contact stop layer over the removable gate electrode and the substrate, removing a portion of the self aligned contact stop layer over the removable gate electrode and the electrode itself leaving an opening, forming a replacement gate electrode of metal, in the opening, transforming an upper portion of the metal into a dielectric layer, and forming a self aligned contact. Embodiments include forming the contact stop layer of a dielectric material, e.g., a hafnium oxide, an aluminum oxide, or a silicon carbide and transforming the upper portion of the metal into a dielectric layer by oxidation, fluorination, or nitridation. Embodiments also include forming a hardmask layer over the removable gate electrode to protect the electrode during silicidation in source/drain regions of the semiconductor device.

    摘要翻译： 具有替换栅电极和集成自对准触点的半导体器件由栅极电介质层和栅极线与触点之间的电隔离特性提高而形成。 实施例包括在衬底上形成可移除的栅电极，在可移除的栅电极和衬底之上形成自对准的接触止动层，在可移除的栅极电极和电极本身上移除一部分自对准接触停止层，留下开口， 在开口中形成金属的替代栅电极，将金属的上部转化成电介质层，并形成自对准的接触。 实施例包括形成电介质材料例如氧化铪，氧化铝或碳化硅的接触停止层，并通过氧化，氟化或氮化将金属的上部转化成电介质层。 实施例还包括在可移除的栅极电极上形成硬掩模层，以在半导体器件的源极/漏极区域中的硅化期间保护电极。