公开(公告)号：US06891275B2

公开(公告)日：2005-05-10

申请号：US10624787

申请日：2003-07-21

申请人： Ryan Lane ,  Edward Reyes ,  Mark Veatch ,  Tom Gregorich

发明人： Ryan Lane ,  Edward Reyes ,  Mark Veatch ,  Tom Gregorich

IPC分类号： H01L23/498 ,  H01L29/40

CPC分类号： H01L23/49838 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/49171 ,  H01L2224/49433 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10162 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： An area array package comprising a die attach area for attaching a die to a substrate, a network of staggered bond fingers, and a network of bond islands for coupling bond wires between the bond islands and die bond pads is provided. A network of package leads, for example, a network of solder balls in a ball grid array, is depopulated to permit greater trace route flexibility and via placement within the substrate. Stacked die and multi-chip packages are also disclosed. A method for accommodating a high pin-count die in an area array package is also included.

摘要翻译： 提供了一种区域阵列封装，其包括用于将管芯附接到衬底的管芯附着区域，交错键合指状物的网络和用于耦合接合岛和管芯接合焊盘之间的接合线的接合岛网络。 封装引线的网络，例如，球栅阵列中的焊球网络被排挤，以允许更大的迹线路径灵活性和通孔放置在基板内。 还公开了堆叠管芯和多芯片封装。 还包括用于容纳区域阵列封装中的高引脚数管芯的方法。

公开(公告)号：US06762495B1

公开(公告)日：2004-07-13

申请号：US10393666

申请日：2003-03-20

申请人： Edward Reyes ,  Ryan Lane ,  Tiona Marburger ,  Tom Gregorich

发明人： Edward Reyes ,  Ryan Lane ,  Tiona Marburger ,  Tom Gregorich

IPC分类号： H01L2348

CPC分类号： H01L23/562 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49838 ,  H01L2224/16225 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/3511 ,  H05K3/3436 ,  H05K2201/09781 ,  Y02P70/613 ,  H01L2224/0401

摘要： An area area package includes a plurality of solder balls not used as electrical connectors. These non-connected solder balls, or “dummy balls,” provide protection to solder balls connected to live pins and therefore increase reliability of the area array package. The dummy balls may be placed in the corners, along the diagonals or in other high stress location on the area array package. To further increase reliability, a continuous copper ball land pad may be used to connect each group of corner dummy balls. Continuous copper pads help to reduce stress on the dummy balls. For center-depopulated BGA packages, an array of dummy balls may be used in the center of the package to prevent substrate bending and improve drop test reliability.

摘要翻译： 区域封装包括不用作电连接器的多个焊球。 这些非连接的焊球或“虚拟球”为连接到活针的焊球提供保护，因此增加了区域阵列封装的可靠性。 虚拟球可以沿着对角线或在区域阵列包装上的其他高应力位置放置在拐角处。 为了进一步提高可靠性，可以使用连续的铜球焊盘来连接每组角落假球。 连续铜垫有助于减轻虚拟球的压力。 对于中心放电的BGA封装，可以在封装的中心使用一组虚拟球，以防止基板弯曲并提高跌落测试的可靠性。

公开(公告)号：USD856053S1

公开(公告)日：2019-08-13

申请号：US29607724

申请日：2017-06-15

申请人： Edward Reyes

设计人： Edward Reyes

公开(公告)号：US06680219B2

公开(公告)日：2004-01-20

申请号：US09932160

申请日：2001-08-17

申请人： Edward Reyes ,  Fifin Irzhann

发明人： Edward Reyes ,  Fifin Irzhann

IPC分类号： H01L2148

CPC分类号： H01L24/49 ,  H01L24/48 ,  H01L25/0652 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19043 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

摘要： An integrated circuit package is constructed by attaching lower dies to a substrate that has bond fingers deposited on its surface. One lower die and its associated bond fingers are located offset from the center of the substrate. The lower dies are electrically coupled to the substrate's bond fingers with lower bond wires. An upper die is stacked on at least one of the lower dies. The upper die is electrically coupled, with bond wires, to the lower die upon which it is mechanically coupled. Each of the lower dies may be coupled to the other lower die with bond wire bridges that span the lower bond wires. The upper die may be electrically coupled, with bond wire bridges, to any or all of the lower dies.

摘要翻译： 通过将下模连接到具有粘结指状物的表面上沉积的基板构成集成电路封装。 一个下模及其相关联的粘合指状物位于从基板的中心偏移的位置。 下模具与下部接合线电连接到基板的键​​合指状物。 上模具堆叠在至少一个下模具上。 上模具与接合线电耦合到与其机械耦合的下模具。 每个下模具可以与跨接下部接合线的接合线桥接件联接到另一个下模具。 上模可以与接合线桥接电耦合到任何或所有下模。

公开(公告)号：USD856054S1

公开(公告)日：2019-08-13

申请号：US29608955

申请日：2017-06-27

申请人： Edward Reyes

设计人： Edward Reyes

公开(公告)号：USD820010S1

公开(公告)日：2018-06-12

申请号：US29589091

申请日：2016-12-28

申请人： Edward Reyes

设计人： Edward Reyes

公开(公告)号：US06787901B2

公开(公告)日：2004-09-07

申请号：US10282795

申请日：2002-10-28

申请人： Edward Reyes ,  Fifin Irzhann

发明人： Edward Reyes ,  Fifin Irzhann

IPC分类号： H01L2334

CPC分类号： H01L24/49 ,  H01L24/48 ,  H01L25/0652 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19043 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

摘要： An integrated circuit package is constructed by attaching lower dies to a substrate that has bond fingers deposited on its surface. One lower die and its associated bond fingers are located offset from the center of the substrate. The lower dies are electrically coupled to the substrate's bond fingers with lower bond wires. An upper die is stacked on at least one of the lower dies. The upper die is electrically coupled, with bond wires, to the lower die upon which it is mechanically coupled. Each of the lower dies may be coupled to the other lower die with bond wire bridges that span the lower bond wires. The upper die may be electrically coupled, with bond wire bridges, to any or all of the lower dies.

公开(公告)号：US20110195223A1

公开(公告)日：2011-08-11

申请号：US12703821

申请日：2010-02-11

申请人： Omar J. Bchir ,  John P. Holmes ,  Edward Reyes

发明人： Omar J. Bchir ,  John P. Holmes ,  Edward Reyes

IPC分类号： B32B3/24 ,  B05D5/00

CPC分类号： H01L23/49816 ,  H01L21/481 ,  H01L24/16 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81191 ,  H01L2924/01327 ,  H01L2924/14 ,  H01L2924/15311 ,  H05K3/3452 ,  H05K2201/0191 ,  H05K2201/10674 ,  Y10T428/24331 ,  H01L2924/00 ,  H01L2924/014

摘要： A substrate including a die side interconnect pattern having a first solder mask thickness, and a board side interconnect pattern having a second solder mask thickness, where the second thickness is greater than the first thickness. Fabrication process using dry film solder mask can apply a first laminate thickness forming a die side solder mask, and a second laminate thickness forming a board side solder mask; the second thickness being greater than the first thickness. Fabrication process using a liquid solder resist can apply a first number of passes of solder resist forming a die side solder mask, and a second number of passes of solder resist forming a board side solder mask, where the board side thickness is greater than the die side thickness.

摘要翻译： 包括具有第一焊料掩模厚度的管芯侧互连图案的衬底和具有第二焊料掩模厚度的板侧互连图案，其中第二厚度大于第一厚度。 使用干膜焊接掩模的制造工艺可以应用形成裸片侧焊料掩模的第一层压厚度和形成板侧焊料掩模的第二层压体厚度; 第二厚度大于第一厚度。 使用液体阻焊剂的制造工艺可以应用形成管芯侧焊料掩模的阻焊剂的第一数量通路，以及形成板侧焊料掩模的第二数量的阻焊剂，其中板侧厚度大于管芯 侧厚。