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    Memory device
    3.
    发明授权
    Memory device 有权
    内存设备

    公开(公告)号：US09075742B2

    公开(公告)日：2015-07-07

    申请号：US13360989

    申请日：2012-01-30

    申请人： Masaya Tarui ,  Tatsunori Kanai ,  Yutaka Yamada ,  Hideki Yoshida

    发明人： Masaya Tarui ,  Tatsunori Kanai ,  Yutaka Yamada ,  Hideki Yoshida

    IPC分类号： G11C29/00 ,  G06F11/10 ,  G11C29/04

    CPC分类号： G06F11/1048 ,  G11C2029/0411

    摘要： According to one embodiment, a memory device comprises a writing device that writes data bits, check bits for error corrections, and overhead bit(s) into a memory, each bit of the overhead bit(s) corresponding to each group of bit group(s) including at least one bit of the data bits and/or the check bits, each bit of the overhead bit(s) indicating whether the corresponding bit group has been inverted, a reading unit that reads the data bits, the check bits, and the overhead bit(s) from the memory, a correcting unit that corrects an error in the data bits and overhead bit(s) read from the memory, based on the check bits, and an inverting unit that inverts the data bits contained in the bit group corresponding to the overhead bit and outputs the inverted data bits as data read from the memory when the error-corrected overhead bit indicates that inversion has been performed.

    摘要翻译： 根据一个实施例，存储器件包括写数据位，用于纠错的校验位和开销位到存储器中的写入设备，每个比特组对应于每组比特组（ s）包括数据位和/或校验位的至少一位，开销位的每个位表示相应的位组是否已被反相，读取单元读取数据位，校验位， 以及来自存储器的开销位，校正单元，其基于校验位校正从存储器读取的数据位和开销位中的错误，以及反相单元，其将包含在存储器中的数据位反相 所述比特组对应于所述开销比特，并且当所述经纠错的开销比特指示已经执行了反转时，将所述反相的数据比特作为从所述存储器读取的数据输出。

    Apparatus and method for controlling power state transitions based on timer events
    4.
    发明授权
    Apparatus and method for controlling power state transitions based on timer events 有权
    基于定时器事件控制功率状态转换的装置和方法

    公开(公告)号：US08453002B2

    公开(公告)日：2013-05-28

    申请号：US13219332

    申请日：2011-08-26

    申请人： Hideki Yoshida

    发明人： Hideki Yoshida

    IPC分类号： G06F1/00 ,  G06F1/26 ,  G06F1/32 ,  G06F9/44 ,  G06F13/24

    CPC分类号： G06F1/3203 ,  G06F9/4893 ,  Y02D10/24

    摘要： According to one embodiment, an electronic apparatus includes a first power saver, a second power saver and a controller. The first power saver executes switching from an operable condition to a first power saving state. The second power saver executes switching from the first state to a second state in which power consumption is smaller than that in the first state. The controller determines whether timer event processing executable in the first state is scheduled within a predetermined period of time when the switching from the operable condition to the second state is required, and controls the first power saver and the second power saver so as to execute switching to the first state and maintains the first state without switching to the second state, when the timer event processing is scheduled within the predetermined period of time.

    摘要翻译： 根据一个实施例，电子设备包括第一节电器，第二节电器和控制器。 第一节电器执行从可操作状态切换到第一省电状态。 第二节电器执行从第一状态切换到功耗小于第一状态的第二状态。 控制器确定是否需要在从可操作状态切换到第二状态的预定时间段内调度处于第一状态的定时器事件处理，并且控制第一节电器和第二节电器以执行切换 并且在预定时间段内调度定时器事件处理时，保持第一状态而不切换到第二状态。

    MEMORY DEVICE
    5.
    发明申请
    MEMORY DEVICE 有权
    内存设备

    公开(公告)号：US20120131418A1

    公开(公告)日：2012-05-24

    申请号：US13360989

    申请日：2012-01-30

    申请人： Masaya Tarui ,  Tatsunori Kanai ,  Yutaka Yamada ,  Hideki Yoshida

    发明人： Masaya Tarui ,  Tatsunori Kanai ,  Yutaka Yamada ,  Hideki Yoshida

    IPC分类号： G11C29/52 ,  G06F11/10

    CPC分类号： G06F11/1048 ,  G11C2029/0411

    摘要： According to one embodiment, a memory device comprises a writing device that writes data bits, check bits for error corrections, and overhead bit(s) into a memory, each bit of the overhead bit(s) corresponding to each group of bit group(s) including at least one bit of the data bits and/or the check bits, each bit of the overhead bit(s) indicating whether the corresponding bit group has been inverted, a reading unit that reads the data bits, the check bits, and the overhead bit(s) from the memory, a correcting unit that corrects an error in the data bits and overhead bit(s) read from the memory, based on the check bits, and an inverting unit that inverts the data bits contained in the bit group corresponding to the overhead bit and outputs the inverted data bits as data read from the memory when the error-corrected overhead bit indicates that inversion has been performed.

    摘要翻译： 根据一个实施例，存储器件包括写数据位，用于纠错的校验位和开销位到存储器中的写入设备，每个比特组对应于每组比特组（ s）包括数据位和/或校验位的至少一位，开销位的每个位表示相应的位组是否已被反相，读取单元读取数据位，校验位， 以及来自存储器的开销位，校正单元，其基于校验位校正从存储器读取的数据位和开销位中的错误，以及反相单元，其将包含在存储器中的数据位反相 所述比特组对应于所述开销比特，并且当所述经纠错的开销比特指示已经执行了反转时，将所述反相的数据比特作为从所述存储器读取的数据输出。

    COMPUTER SYSTEM AND COMPUTER SYSTEM CONTROL METHOD
    6.
    发明申请
    COMPUTER SYSTEM AND COMPUTER SYSTEM CONTROL METHOD 有权
    计算机系统和计算机系统控制方法

    公开(公告)号：US20120117407A1

    公开(公告)日：2012-05-10

    申请号：US13310892

    申请日：2011-12-05

    申请人： Tatsunori Kanai ,  Yutaka Yamada ,  Hideki Yoshida ,  Masaya Tarui

    发明人： Tatsunori Kanai ,  Yutaka Yamada ,  Hideki Yoshida ,  Masaya Tarui

    IPC分类号： G06F1/32

    CPC分类号： G06F1/3275 ,  Y02D10/13 ,  Y02D10/14

    摘要： According to one embodiment, a computer system comprises a first memory that stores a first program, a second memory that stores a second program or data, a processor, a first and a second power control circuits. The first power control circuit causes the first memory to operate at a first power consumption when detecting change of an input signal to the processor, and causes the first memory to operate at a second power consumption smaller than the first power consumption and transmits a temporary halt instruction to the processor when the execution of the first program or the second program by the processor is completed. The second power control circuit causes the second memory to operate at a third power consumption before the processor executes the second program, reads or writes the data.The second memory accepts read and write operations while operating at the third power consumption.

    摘要翻译： 根据一个实施例，计算机系统包括存储第一程序的第一存储器，存储第二程序或数据的第二存储器，处理器，第一和第二功率控制电路。 当检测到对处理器的输入信号的变化时，第一功率控制电路使得第一存储器以第一功率消耗操作，并且使得第一存储器以比第一功耗小的第二功耗工作，并且发送暂时停止 当处理器执行第一程序或第二程序完成时，指令到处理器。 第二功率控制电路使得第二存储器在处理器执行第二程序之前以第三功耗操作，读取或写入数据。 第二个存储器在以第三次功耗运行的同时接受读写操作。

    LED REFLECTING PLATE AND LED DEVICE
    7.
    发明申请
    LED REFLECTING PLATE AND LED DEVICE 审中-公开
    LED反光板和LED器件

    公开(公告)号：US20100032693A1

    公开(公告)日：2010-02-11

    申请号：US12581828

    申请日：2009-10-19

    申请人： Ryouji Sugiura ,  Hideki Yoshida

    发明人： Ryouji Sugiura ,  Hideki Yoshida

    IPC分类号： H01L33/00

    CPC分类号： H01L33/60 ,  H01L33/62 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/01004 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12041 ,  H01L2924/00014

    摘要： A recess is formed in a land (2) of an LED reflecting plate (1) formed of a metal plate. The recess comprises a flat LED chip mounting portion (7) and a reflecting portion (8) inclined with respect to the LED chip mounting portion (7). The LED reflecting plate (1) is mounted on a printed wiring board (25) such that the land (2) is fitted in a first through hole (18). An LED chip (27) mounted on the LED chip mounting portion (7) is connected to a terminal portion (22) formed on the printed wiring board (25). The printed wiring board (25) is diced along a third through hole (19) to form an LED device (30) as one unit. With this arrangement, heat radiation properties and reflecting efficiency of the LED device (30) can be improved, and the manufacturing cost can be decreased.

    摘要翻译： 在由金属板形成的LED反射板（1）的平台（2）中形成凹部。 凹部包括平坦的LED芯片安装部分（7）和相对于LED芯片安装部分（7）倾斜的反射部分（8）。 LED反射板（1）安装在印刷电路板（25）上，使得焊盘（2）装配在第一通孔（18）中。 安装在LED芯片安装部分（7）上的LED芯片（27）连接到形成在印刷电路板（25）上的端子部分（22）。 印刷电路板（25）沿着第三通孔（19）切割，形成作为一个单元的LED器件（30）。 利用这种布置，可以提高LED装置（30）的散热特性和反射效率，并且可以降低制造成本。

    Data processor capable of preventing data overflows and underflows
    9.
    发明授权
    Data processor capable of preventing data overflows and underflows 失效
    能够防止数据溢出和下溢的数据处理器

    公开(公告)号：US07389318B2

    公开(公告)日：2008-06-17

    申请号：US10432881

    申请日：2001-11-28

    申请人： Hideki Yoshida ,  Jin Sato ,  Kazuyuki Ikeda ,  Takashi Norizuki ,  Kenichi Sakusabe ,  Daisuke Kawaguchi ,  Munehiro Yoshikawa

    发明人： Hideki Yoshida ,  Jin Sato ,  Kazuyuki Ikeda ,  Takashi Norizuki ,  Kenichi Sakusabe ,  Daisuke Kawaguchi ,  Munehiro Yoshikawa

    IPC分类号： G06F15/16

    CPC分类号： H04N21/4307 ,  H04N5/04 ,  H04N5/38 ,  H04N5/4401 ,  H04N21/23406 ,  H04N21/44004 ,  H04N21/478

    摘要： A data processing apparatus constituting a low-cost audio/video data transmission and reception system is disclosed. A reception buffer monitoring circuit 21 monitors the size of receiver data being accumulated in a reception buffer 6. When the size of accumulated data is found to become higher than a high threshold, the circuit 21 causes a reception clock generation circuit 8 to generate a reception clock with a higher frequency. When the accumulated data size becomes lower than a low threshold, the reception clock is generated with a lower frequency. Based on the reception clock fed from the reception clock generation circuit 8, an audio/video decoder 7 decodes the audio/video data coming from the reception buffer 6. This invention applies advantageously to a television transmission and reception system for transmitting and receiving TV broadcast signals.

    摘要翻译： 公开了构成低成本音频/视频数据发送和接收系统的数据处理装置。 接收缓冲器监视电路21监视在接收缓冲器6中积累的接收机数据的大小。 当发现累加数据的大小变得高于高阈值时，电路21使接收时钟产生电路8产生具有较高频率的接收时钟。 当累积的数据大小变得低于低阈值时，以较低的频率生成接收时钟。 基于从接收时钟发生电路8馈送的接收时钟，音频/视频解码器7解码来自接收缓冲器6的音频/视频数据。 本发明有利地适用于用于发送和接收TV广播信号的电视发射和接收系统。