FAN-OUT SEMICONDUCTOR PACKAGE
    1.
    发明申请

    公开(公告)号:US20190019757A1

    公开(公告)日:2019-01-17

    申请号:US15819541

    申请日:2017-11-21

    Abstract: A fan-out semiconductor package includes: a semiconductor chip; an encapsulant encapsulating at least portions of the semiconductor chip; and a first connection member disposed on the semiconductor chip and including a first redistribution layer electrically connected to the connection pads and a second redistribution layer electrically connected to the connection pads and disposed on the first redistribution layer. The first redistribution layer includes a first pattern having a plurality of degassing holes, the second redistribution layer includes a second pattern having a first line portion having a first line width and a second line portion connected to the first line portion and having a second line width greater than the first line width, and the second line portion overlaps at least one of the plurality of degassing holes when being projected in a direction perpendicular to the active surface.

    MULTILAYER ELECTRONIC COMPONENT
    4.
    发明申请

    公开(公告)号:US20250125097A1

    公开(公告)日:2025-04-17

    申请号:US18775131

    申请日:2024-07-17

    Abstract: A multilayer electronic component includes a body including a dielectric layer and first and second internal electrodes, the body having a first surface and a second surface opposing each other in a first direction, a third surface and a fourth surface opposing each other in a second direction, and a fifth surface and a sixth surface opposing each other in a third direction, an external electrode including a lower electrode layer, the lower electrode layer disposed between extension lines of the first and second surfaces, an upper electrode layer disposed on the lower electrode layer, the upper electrode layer disposed to extend onto a portion of the first and the second surfaces, and a glass layer disposed between the lower and upper electrode layers. The lower electrode layer includes Ag and a first glass. The upper electrode layer includes Cu and a second glass.

    MULTILAYER ELECTRONIC COMPONENT
    7.
    发明申请

    公开(公告)号:US20250132093A1

    公开(公告)日:2025-04-24

    申请号:US18781000

    申请日:2024-07-23

    Abstract: A multilayer electronic component according to an embodiment of the present disclosure includes a body including a dielectric layer and an internal electrode; and an external electrode including an electrode layer disposed on the body and connected to the internal electrode, and a plating layer disposed on the electrode layer, wherein the electrode layer includes a connection electrode layer including copper (Cu) and glass, and a band electrode layer including silver (Ag) and glass, and the external electrode further includes a conductive resin layer disposed between the band electrode layer and the plating layer and including a conductive metal and a resin.

    MULTILAYER CERAMIC CAPACITOR AND METHOD OF MANUFACTURING THE SAME

    公开(公告)号:US20210166881A1

    公开(公告)日:2021-06-03

    申请号:US16877902

    申请日:2020-05-19

    Abstract: A multilayer ceramic capacitor includes a ceramic body including a dielectric layer, a plurality of first and second internal electrodes disposed inside the ceramic body, exposed to the first and second surfaces, and having ends exposed to the third or fourth surface, and a first side margin portion and a second side margin portion disposed on side portions of the plurality of first and second internal electrodes exposed to the first and second surfaces. A ratio Db/Da satisfies 1.00 to 1.07, inclusive, where ‘Db’ is a distance, in a stacking direction of the dielectric layer, between both end points of respective edge regions of the first side margin portion and the second side margin portion, and ‘Da’ is a distance in a central region of the ceramic body in the stacking direction.

Patent Agency Ranking