公开(公告)号：USD717254S1

公开(公告)日：2014-11-11

申请号：US29450494

申请日：2013-03-18

Applicant: Samsung Electro-Mechanics Co., Ltd.

Designer： Eun Jung Jo ,  Job Ha ,  Kee Ju Um ,  Sun Woo Yun ,  Chang Seob Hong ,  Suk Ho Kee ,  Sung Man Pang ,  Jun Ho Lee ,  Kyu Hwan Oh

公开(公告)号：US20140118956A1

公开(公告)日：2014-05-01

申请号：US13830122

申请日：2013-03-14

Applicant: Samsung Electro-Mechanics Co., Ltd.

Inventor： Kwang Soo KIM ,  Si Joong Yang ,  Bum Seok Suh ,  Young Hoon Kwak ,  Job Ha

IPC: H05K1/18

CPC classification number: H01L23/043 ,  H01L23/049 ,  H01L23/14 ,  H01L23/3735 ,  H01L24/36 ,  H01L24/37 ,  H01L24/40 ,  H01L2224/371 ,  H01L2224/37147 ,  H01L2224/37155 ,  H01L2224/3716 ,  H01L2224/37599 ,  H01L2224/40095 ,  H01L2224/40137 ,  H01L2224/40225 ,  H01L2224/48091 ,  H01L2924/12041 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/19105 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Disclosed herein is an all-in-one power semiconductor module including a plurality of first semiconductor devices formed on a substrate; a housing molded and formed to include bridges formed across upper portions of the plurality of first semiconductor devices; and a plurality of lead members integrally formed with the housing and electrically connecting the plurality of first semiconductor devices and the substrate.According to the present invention, reliability can be improved by increasing bonding areas and bonding strength of semiconductor devices as well as processibilty can be enhanced and failure is reduced by adjusting a step difference with respect to an arrangement and height of the semiconductor devices. Further, a processing time resulting from an omission of a wire bonding process is reduced.

Abstract translation: 这里公开了一种一体化功率半导体模块，其包括形成在基板上的多个第一半导体器件; 模制并形成为包括形成在多个第一半导体器件的上部的桥的壳体; 以及多个引线部件，与所述壳体一体地形成并且电连接所述多个第一半导体器件和所述基板。 根据本发明，通过增加接合面积和半导体器件的接合强度可以提高可靠性，并且通过调节相对于半导体器件的布置和高度的台阶差，可以提高加工性并降低故障。 此外，减少了由于省略引线键合处理而产生的处理时间。

公开(公告)号：USD717256S1

公开(公告)日：2014-11-11

申请号：US29450512

申请日：2013-03-18

Applicant: Samsung Electro-Mechanics Co., Ltd.

Designer： Young Ho Sohn ,  Job Ha ,  Jang Man Kim ,  Sung Man Pang ,  Sun Woo Yun ,  Suk Ho Lee ,  Hyo Jin Lee ,  Kyu Hwan Oh ,  Jae Hoon Park

公开(公告)号：US10811358B2

公开(公告)日：2020-10-20

申请号：US16513171

申请日：2019-07-16

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Job Ha ,  Sung Hyun Kim ,  Ji Na Jeung

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/14 ,  H01L23/15

Abstract: A semiconductor package includes an organic frame having first and second surfaces opposing each other, having a cavity, and having a wiring structure connecting the first and second surfaces, a connection structure disposed on the first surface of the organic frame and having a first redistribution layer connected to the wiring structure, at least one inorganic interposer having first and second surfaces, and having an interconnection wiring connecting the first and second surfaces of the at least one inorganic interposer to each other, an encapsulant encapsulating at least a portion of the at least one inorganic interposer, an insulating layer disposed on the second surface of the organic frame and the second surface of the at least one inorganic interposer, a second redistribution layer having portions provided as a plurality of pads, and at least one semiconductor chip having connection electrodes respectively connected to the plurality of pads.

公开(公告)号：USD717253S1

公开(公告)日：2014-11-11

申请号：US29450492

申请日：2013-03-18

Applicant: Samsung Electro-Mechanics Co., Ltd.

Designer： Eun Jung Jo ,  Jin Suk Son ,  Job Ha ,  Jae Hoon Park ,  Chang Seob Hong ,  Joon Hyung Cho ,  In Wha Jeong ,  Young Hoon Kwak ,  Chang Jae Heo

公开(公告)号：US20150228567A1

公开(公告)日：2015-08-13

申请号：US14273306

申请日：2014-05-08

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Job Ha

IPC: H01L23/495 ,  H05K1/02

CPC classification number: H05K1/0296 ,  H01L23/3735 ,  H01L23/49575 ,  H01L23/49811 ,  H01L23/49838 ,  H01L2224/48091 ,  H01L2224/48139 ,  H01L2224/48247 ,  H01L2224/4903 ,  H01L2224/49171 ,  H01L2924/13055 ,  H05K1/056 ,  H05K3/0052 ,  H05K2201/09781 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Disclosed herein are a package substrate and a semiconductor package using the same. The package substrate includes a circuit area in which a circuit pattern is formed and a dummy area in which a dummy pattern is formed to surround the circuit area.

Abstract translation: 这里公开了封装基板和使用该基板的半导体封装。 封装衬底包括其中形成电路图案的电路区域和形成虚拟图案以围绕电路区域的虚拟区域。

公开(公告)号：US20140138839A1

公开(公告)日：2014-05-22

申请号：US13735125

申请日：2013-01-07

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Job Ha ,  Sang Hee Park

IPC: H01L23/48

CPC classification number: H01L23/3735 ,  H01L23/36 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/29101 ,  H01L2224/32013 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2924/00014 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2224/45099 ,  H01L2924/00012

Abstract: Disclosed herein is a power semiconductor module including a substrate having a first metal conductive track formed on one surface thereof, and a base plate made of a metal and solder-joined to the substrate in the first metal conductive track region, wherein a first uneven pattern is formed in the solder junction region formed between the substrate and the base plate.

Abstract translation: 本发明公开了一种功率半导体模块，其包括具有在其一个表面上形成的第一金属导电轨道的基板和由第一金属导电轨道区域中的与金属焊接接合的基板，其中第一不平坦图案 形成在形成在基板和基板之间的焊接区域中。

公开(公告)号：US09455207B2

公开(公告)日：2016-09-27

申请号：US13830122

申请日：2013-03-14

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Kwang Soo Kim ,  Si Joong Yang ,  Bum Seok Suh ,  Young Hoon Kwak ,  Job Ha

IPC: H01L23/043 ,  H01L23/049 ,  H01L23/00 ,  H01L23/14 ,  H01L23/373

CPC classification number: H01L23/043 ,  H01L23/049 ,  H01L23/14 ,  H01L23/3735 ,  H01L24/36 ,  H01L24/37 ,  H01L24/40 ,  H01L2224/371 ,  H01L2224/37147 ,  H01L2224/37155 ,  H01L2224/3716 ,  H01L2224/37599 ,  H01L2224/40095 ,  H01L2224/40137 ,  H01L2224/40225 ,  H01L2224/48091 ,  H01L2924/12041 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/19105 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Disclosed herein is an all-in-one power semiconductor module including a plurality of first semiconductor devices formed on a substrate; a housing molded and formed to include bridges formed across upper portions of the plurality of first semiconductor devices; and a plurality of lead members integrally formed with the housing and electrically connecting the plurality of first semiconductor devices and the substrate.According to the present invention, reliability can be improved by increasing bonding areas and bonding strength of semiconductor devices as well as processibilty can be enhanced and failure is reduced by adjusting a step difference with respect to an arrangement and height of the semiconductor devices. Further, a processing time resulting from an omission of a wire bonding process is reduced.

Abstract translation: 根据本发明，通过增加接合面积和半导体器件的接合强度可以提高可靠性，并且通过调节相对于半导体器件的布置和高度的台阶差，可以提高加工性并降低故障。 此外，减少了由于省略引线键合处理而产生的处理时间。

公开(公告)号：US09099451B2

公开(公告)日：2015-08-04

申请号：US14275565

申请日：2014-05-12

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Job Ha

IPC: H01L23/495 ,  H01L21/50 ,  H01L21/48 ,  H01L23/373

CPC classification number: H01L23/49503 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/373 ,  H01L23/3737 ,  H01L23/49531 ,  H01L23/49548 ,  H01L23/49555 ,  H01L23/49562 ,  H01L23/49568 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/73265 ,  H01L2924/13055 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Disclosed herein are a power module package and a method of manufacturing the same. The power module package includes first and second semiconductor devices mounted on sides of first and second lead frames, ends of which are separated from each other, respectively, a support pin corresponding to a mounting position of the first semiconductor device and formed adjacent to a lower portion of the first lead frame, and a molding portion formed to cover portions of the first and second lead frames and the first and second semiconductor devices.

Abstract translation: 这里公开了功率模块封装及其制造方法。 功率模块封装包括安装在第一和第二引线框架的侧面上的第一和第二半导体器件，其端部分别彼此分开，对应于第一半导体器件的安装位置并形成在下部 第一引线框架的一部分和形成为覆盖第一引线框架和第二引线框架以及第一和第二半导体器件的部分的模制部分。

公开(公告)号：US20150145123A1

公开(公告)日：2015-05-28

申请号：US14314826

申请日：2014-06-25

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Job Ha

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/49811 ,  H01L21/4853 ,  H01L21/56 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/3735 ,  H01L23/49844 ,  H01L25/072 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/73265 ,  H01L2924/13055 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Disclosed herein are a power semiconductor module and a method of manufacturing the same. The power semiconductor module includes: a substrate on which a semiconductor device is mounted; a pin positioned on the substrate and having one side electrically connected to the substrate; and a molding part formed to cover a portion of the pin and the substrate and the semiconductor device, wherein the molding part has a pin insertion opening.

Abstract translation: 这里公开了功率半导体模块及其制造方法。 功率半导体模块包括：其上安装有半导体器件的衬底; 位于所述基板上并具有与所述基板电连接的一侧的销; 以及模制部件，其形成为覆盖所述销和所述基板以及所述半导体器件的一部分，其中所述模制部件具有销插入口。