Abstract:
Disclosed herein is an all-in-one power semiconductor module including a plurality of first semiconductor devices formed on a substrate; a housing molded and formed to include bridges formed across upper portions of the plurality of first semiconductor devices; and a plurality of lead members integrally formed with the housing and electrically connecting the plurality of first semiconductor devices and the substrate.According to the present invention, reliability can be improved by increasing bonding areas and bonding strength of semiconductor devices as well as processibilty can be enhanced and failure is reduced by adjusting a step difference with respect to an arrangement and height of the semiconductor devices. Further, a processing time resulting from an omission of a wire bonding process is reduced.
Abstract:
An inverter includes an inverter unit including at least one inverter arm having at least one high side switch and at least one low side switch connected to each other in series between a ground and an input power terminal providing input power having a preset voltage level, and switching the input power to output AC power; and a high voltage gate driving circuit unit including at least one high voltage gate driving unit having a plurality of high voltage gate drivers connected in series between an input terminal of an instruction signal requesting a switching control of the inverter unit and an output terminal of a control signal controlling switching of the inverter unit, such that switching of the high side switch is controlled, and voltage generated at the time of switching the high side switch is divided and applied to the plurality of high voltage gate drivers.
Abstract:
There is provided a power semiconductor module in which power semiconductor elements, integration of which may be difficult due to heating, are modularized. The power semiconductor module includes: a heat dissipation substrate electrically connected to a common connection terminal; and a plurality of electronic elements disposed on the heat dissipation substrate, wherein the electronic elements have varying spaces therebetween.
Abstract:
Disclosed herein is a unit power module including: a first semiconductor chip having one surface on which a 1-1-th electrode and a 1-2-th electrode spaced apart from the 1-1-th electrode are formed and the other surface on which a 1-3-th electrode is formed, a second semiconductor chip having one surface on which a 2-1-th electrode is formed and the other surface on which a 2-2-th electrode is formed, a first metal plate contacting the 1-1-th electrode of the first semiconductor chip and the 2-1-th electrode of the second semiconductor chip, a second metal plate contacting the 1-2-th electrode of the first semiconductor chip and spaced apart from the first metal plate, a third metal plate contacting the 1-3-th electrode of the first semiconductor chip and the 2-2-th electrode of the second semiconductor chip, and a sealing member formed to surround the first metal plate, the second metal plate, and the third metal plate.
Abstract:
Disclosed herein is a power module package including: a substrate including a metal layer, a first insulation layer formed on the metal layer, a first circuit pattern formed on the first insulation layer and including a first pad and a second pad spaced apart from the first pad, a second insulation layer formed on the first insulation layer to cover the first circuit pattern, and a second circuit pattern formed on the second insulation layer and including a third pad formed on a location corresponding to the first pad and a fourth pad spaced apart from the third pad; a semiconductor chip mounted on the second circuit pattern; one end being electrically connected to the semiconductor chip, and another end protruding from the outside, wherein the first pad and the third pad, and the second pad and the fourth pad have different polarities.
Abstract:
There is provided a driving apparatus for driving an interleaved power factor correction circuit including a first main switch and a second main switch performing a switching operation with a predetermined phase difference and a first auxiliary switch and a second auxiliary switch forming a transformation path for surplus power existing before an ON operation of the first main switch and a second main switch, respectively, including: an input unit obtaining an input signal; a current sensing unit obtaining information regarding a current of the interleaved power factor correction circuit; and an output unit outputting a first control signal with respect to the first main switch, a third control signal with respect to the second main switch, a second control signal with respect to the first auxiliary switch, and a fourth control signal with respect to the second auxiliary switch, based on the input signal and the current information.
Abstract:
There is provided an inverter including: an inverter unit including at least one inverter arm having a plurality of switches, and switching the input power according to control to output an alternating current power; at least one driving unit including at least one high voltage gate driving unit having a plurality high voltage gate drivers connected to one another in series between an input terminal of an instruction signal instructing a switching control of an inverter unit and an output terminal of a control signal controlling switching of the inverter unit to control switching driving of a high side switch and including at least one low voltage gate driver to control switching driving of a low side switch; and at least one bootstrap unit charging/discharging and dividing a voltage generated at the time of switching the plurality of switches according to switching control of the driving unit.
Abstract:
Disclosed herein is a semiconductor module package, including: a first module including a first heat radiation substrate and one or more first semiconductor elements and having a first N terminal and a first P terminal formed at one end thereof; a second module including a second heat radiation substrate and one or more second semiconductor elements, having a second N terminal and a second P terminal formed at one end thereof, and disposed so as to face the first module; and a first output terminal formed by electrically connecting the first module to the second module.
Abstract:
There is provided a power factor correction circuit including: a main switching unit including a first main switch and a second main switch performing a switching operation to regulate a phase difference between a current and a voltage of input power, respectively; a main inductor unit including a first main inductor and a second main inductor accumulating or discharging energy according to a switching operation of each of the first main switch and the second main switch; a snubber switching unit including a first snubber switch and a second snubber switch providing zero-voltage turn-on conditions to the first main switch and the second main switch, respectively; and a controller controlling a switching operation of the main switching unit and the snubber switching unit.
Abstract:
There is provided a flyback converter, including: a power supply unit supplying input power; a transformer unit including first and second transformers converting first and second primary current from the power supply unit into first and second secondary current, respectively; a main switch unit including first and second main switches respectively intermitting the first and second primary current flowing in respective primary windings of the first and second transformers; an auxiliary switch unit including first and second auxiliary switches forming respective transfer paths for dump power present before the first and second main switches are switched on; and an auxiliary inductor unit including first and second auxiliary inductors respectively adjusting the amount of current flowing in the first and second auxiliary switches during the switching operation thereof, wherein the first and second main switches perform a switching operation while having a predetermined phase difference therebetween.