公开(公告)号：US20140104798A1

公开(公告)日：2014-04-17

申请号：US14055335

申请日：2013-10-16

Applicant: Samsung Electro-Mechanics Co., Ltd.

Inventor： Seung Wook Park ,  Dong Hwan LEE ,  Romero CHRISTIAN ,  Young Do KWEON ,  Jin Gu KIM

IPC: H05K1/11

CPC classification number: H05K1/11 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K1/115 ,  H05K3/4673 ,  H05K2201/09509 ,  H05K2201/09727 ,  Y10T428/24802 ,  H01L2924/00

Abstract: Disclosed herein are a hybrid lamination substrate and a manufacturing method thereof. The hybrid lamination substrate includes: a core layer; at least one first insulating layer that is made of a photosensitive resin material and is formed on an upper portion, a lower portion, or upper and lower portions of the core layer; and at least one second insulating layer that is made of a non-photosensitive resin material and is formed on the upper portion, the lower portion, or the upper and lower portions of the core layer. Further, a package substrate including the same and a manufacturing method of a hybrid lamination substrate are proposed.

Abstract translation: 本文公开了混合层合基板及其制造方法。 混合层压基板包括：芯层; 至少一个第一绝缘层，由感光树脂材料制成并形成在芯层的上部，下部或上下部分上; 以及由非感光性树脂材料制成并且形成在芯层的上部，下部或上下部分上的至少一个第二绝缘层。 此外，提出了包括该封装基板的封装基板和混合层叠基板的制造方法。

公开(公告)号：US20130320561A1

公开(公告)日：2013-12-05

申请号：US13906951

申请日：2013-05-31

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Seung Wook PARK ,  Romero CHRISTIAN ,  Chang Bae LEE ,  Mi Jin PARK

IPC: H01L23/498 ,  H01L21/768

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L21/76877 ,  H01L2924/0002 ,  H05K1/112 ,  H05K1/113 ,  H05K1/115 ,  H05K3/42 ,  H05K2201/09481 ,  H05K2201/0959 ,  H01L2924/00

Abstract: Disclosed herein is a plug via stacked structure including: a through hole plating layer plated on a through hole inner wall and around top and bottom of a through hole at thickness t; a via plug filled in an inner space of the through hole plating layer; a circuit pattern formed over the top and bottom of the through hole plating layer and the via plug and making a thickness t′ formed on the through hole plating layer thicker than a thickness t; and a stacked conductive via filled in a via hole formed on the top of the through hole and formed at thickness α from a top of the circuit pattern, wherein T≦t″+α is satisfied, T represents a sum of the thicknesses t and t′ and t″ is a thickness of a portion of the circuit pattern formed on the via plug.

Abstract translation: 本文公开了一种插头通孔堆叠结构，包括：镀敷在通孔内壁上且贯穿孔的顶部和底部的通孔镀层，厚度为t; 通孔塞，其填充在所述通孔镀层的内部空间中; 形成在通孔镀层和通孔塞的顶部和底部上并形成在厚度t以上的通孔镀层上的厚度t'的电路图案; 以及填充在通孔顶部形成的通孔的叠层导电通孔，其形成为从电路图案的顶部的厚度α，其中T @ t“+α满足，T表示厚度t的和 并且t'和t“是形成在通孔塞上的电路图案的一部分的厚度。

公开(公告)号：US20130133928A1

公开(公告)日：2013-05-30

申请号：US13689031

申请日：2012-11-29

Applicant: Samsung Electro-Mechanics Co., Ltd.

Inventor： Mi Jin PARK ,  Romero CHRISTIAN ,  Seung Wook PARK

IPC: H05K1/02 ,  H05K3/40 ,  H05K3/46

CPC classification number: H05K1/0298 ,  H01L2224/10 ,  H05K1/0237 ,  H05K3/4038 ,  H05K3/4644 ,  H05K2201/09681 ,  H05K2201/09972 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: Disclosed herein is a printed circuit board, including: a core layer; and a plurality of circuit layers stacked on the core layer, wherein one of the circuit layers includes a mesh pattern and a solid pattern, and another of the circuit layers include a first signal pattern opposite to the mesh pattern and a second signal pattern opposite to the solid pattern, the second signal pattern having a high-speed signal line with a higher speed, as compared with the second signal pattern.

Abstract translation: 这里公开了一种印刷电路板，包括：芯层; 以及堆叠在所述芯层上的多个电路层，其中所述电路层中的一个包括网格图案和固体图案，并且所述电路层中的另一个包括与所述网格图案相对的第一信号图案和与所述网格图案相对的第二信号图案 固体图案，第二信号图案具有与第二信号图案相比具有较高速度的高速信号线。