公开(公告)号：US20160198568A1

公开(公告)日：2016-07-07

申请号：US14987291

申请日：2016-01-04

Applicant: Samsung Electro-Mechanics Co., Ltd.

Inventor： Mi Jin PARK ,  Kyoung Moo HARR ,  Seung Wan SHIN

IPC: H05K1/02 ,  H05K1/18 ,  H05K1/11

CPC classification number: H05K3/4682 ,  H05K1/113 ,  H05K1/181 ,  H05K2201/0187

Abstract: A printed circuit board includes a first insulating layer including a first circuit pattern, a second insulating layer including a second circuit pattern, and a dummy pattern disposed in the first insulating layer and the second insulating layer, in which the first and second insulating layers are made of different materials. An electronic component module includes a printed circuit board and an electronic component mounted on the printed circuit board.

Abstract translation: 印刷电路板包括：第一绝缘层，包括第一电路图案，第二绝缘层，包括第二电路图案;以及虚设图案，设置在第一绝缘层和第二绝缘层中，其中第一和第二绝缘层为 由不同的材料制成。 电子部件模块包括印刷电路板和安装在印刷电路板上的电子部件。

公开(公告)号：US20170365567A1

公开(公告)日：2017-12-21

申请号：US15369518

申请日：2016-12-05

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Yun Bog KIM ,  Mi Jin PARK ,  Yeon Seop YU ,  Shang Hoon SEO

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L24/05 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/20 ,  H01L2224/0235 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05008 ,  H01L2224/05569 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05663 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/05671 ,  H01L2224/05673 ,  H01L2224/05676 ,  H01L2224/05678 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2224/20 ,  H01L2224/73204 ,  H01L2924/15153 ,  H01L2924/171 ,  H05K1/186

Abstract: A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface and an inactive surface; an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip; and a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip, wherein the first interconnection member and the second interconnection member each include a redistribution layer electrically connected to the connection pads, the semiconductor chip includes a passivation layer having openings exposing at least portions of the connection pads, the redistribution layer of the second interconnection member is connected to the connection pad through a via, a metal layer is disposed between the connection pad and the via, and the metal layer covers at least a portion of the connection pad.

公开(公告)号：US20150055312A1

公开(公告)日：2015-02-26

申请号：US14250965

申请日：2014-04-11

Applicant: Samsung Electro-Mechanics Co., Ltd.

Inventor： Jeong Ho LEE ,  Mi Jin PARK ,  Chang Bae LEE ,  Young Do KWEON

IPC: H05K1/11 ,  H05K13/04 ,  H05K3/10 ,  B23K1/00 ,  H05K1/18 ,  H05K3/18

CPC classification number: B23K1/0016 ,  B23K2101/42 ,  H01L2224/16225 ,  H01L2924/15311 ,  H05K3/381 ,  H05K3/4602 ,  H05K3/4661 ,  H05K2201/096 ,  H05K2201/10378 ,  H05K2203/041

Abstract: Disclosed herein is an interposer substrate, including: a core layer and a through core via (TCV) penetrating through the core layer; circuit wirings formed on both surfaces of the core layer and a TCV upper pad and a TCV lower pad which are each bonded to upper and lower surfaces of the TCV formed on both surfaces of the core layer; upper insulating layers covering the TCV upper pad and the circuit wiring formed on one surface of the core layer and having the circuit wirings formed on upper surfaces thereof; a stack via penetrating through the upper insulating layers of each layer and having one end connected to the TCV upper pad; and a lower insulating layer covering the TCV lower pad and the circuit wiring formed on the other surface of the core layer and provided with an opening which exposes the TCV lower pad.

Abstract translation: 本发明公开了一种内插衬底，包括：穿透核心层的核心层和穿芯通孔（TCV）; 形成在芯层的两个表面上的电路布线和TCV上焊盘和TCV下焊盘，其各自结合到形成在芯层的两个表面上的TCV的上表面和下表面; 覆盖TCV上焊盘的上绝缘层和形成在芯层的一个表面上并且在其上表面上形成电路布线的电路布线; 通过穿过每层的上绝缘层并且具有连接到TCV上垫的一端的叠层; 以及覆盖TCV下焊盘的下绝缘层和形成在芯层的另一表面上的电路布线，并且设置有暴露TCV下焊盘的开口。

公开(公告)号：US20130320561A1

公开(公告)日：2013-12-05

申请号：US13906951

申请日：2013-05-31

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Seung Wook PARK ,  Romero CHRISTIAN ,  Chang Bae LEE ,  Mi Jin PARK

IPC: H01L23/498 ,  H01L21/768

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L21/76877 ,  H01L2924/0002 ,  H05K1/112 ,  H05K1/113 ,  H05K1/115 ,  H05K3/42 ,  H05K2201/09481 ,  H05K2201/0959 ,  H01L2924/00

Abstract: Disclosed herein is a plug via stacked structure including: a through hole plating layer plated on a through hole inner wall and around top and bottom of a through hole at thickness t; a via plug filled in an inner space of the through hole plating layer; a circuit pattern formed over the top and bottom of the through hole plating layer and the via plug and making a thickness t′ formed on the through hole plating layer thicker than a thickness t; and a stacked conductive via filled in a via hole formed on the top of the through hole and formed at thickness α from a top of the circuit pattern, wherein T≦t″+α is satisfied, T represents a sum of the thicknesses t and t′ and t″ is a thickness of a portion of the circuit pattern formed on the via plug.

Abstract translation: 本文公开了一种插头通孔堆叠结构，包括：镀敷在通孔内壁上且贯穿孔的顶部和底部的通孔镀层，厚度为t; 通孔塞，其填充在所述通孔镀层的内部空间中; 形成在通孔镀层和通孔塞的顶部和底部上并形成在厚度t以上的通孔镀层上的厚度t'的电路图案; 以及填充在通孔顶部形成的通孔的叠层导电通孔，其形成为从电路图案的顶部的厚度α，其中T @ t“+α满足，T表示厚度t的和 并且t'和t“是形成在通孔塞上的电路图案的一部分的厚度。

公开(公告)号：US20130133928A1

公开(公告)日：2013-05-30

申请号：US13689031

申请日：2012-11-29

Applicant: Samsung Electro-Mechanics Co., Ltd.

Inventor： Mi Jin PARK ,  Romero CHRISTIAN ,  Seung Wook PARK

IPC: H05K1/02 ,  H05K3/40 ,  H05K3/46

CPC classification number: H05K1/0298 ,  H01L2224/10 ,  H05K1/0237 ,  H05K3/4038 ,  H05K3/4644 ,  H05K2201/09681 ,  H05K2201/09972 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: Disclosed herein is a printed circuit board, including: a core layer; and a plurality of circuit layers stacked on the core layer, wherein one of the circuit layers includes a mesh pattern and a solid pattern, and another of the circuit layers include a first signal pattern opposite to the mesh pattern and a second signal pattern opposite to the solid pattern, the second signal pattern having a high-speed signal line with a higher speed, as compared with the second signal pattern.

Abstract translation: 这里公开了一种印刷电路板，包括：芯层; 以及堆叠在所述芯层上的多个电路层，其中所述电路层中的一个包括网格图案和固体图案，并且所述电路层中的另一个包括与所述网格图案相对的第一信号图案和与所述网格图案相对的第二信号图案 固体图案，第二信号图案具有与第二信号图案相比具有较高速度的高速信号线。