公开(公告)号：US09431522B2

公开(公告)日：2016-08-30

申请号：US15003288

申请日：2016-01-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungmin Kim ,  Sung-Dae Suk ,  Jaehoo Park ,  Dongho Cha ,  Daewon Ha

IPC: H01L21/84 ,  H01L29/66 ,  H01L21/02 ,  H01L21/308 ,  H01L21/762 ,  H01L29/06

CPC classification number: H01L29/66795 ,  H01L21/02233 ,  H01L21/308 ,  H01L21/76224 ,  H01L21/845 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/6656

Abstract: A method of manufacturing a semiconductor device includes patterning a substrate to form an active fin, forming a sacrificial gate pattern crossing over the active fin on the substrate, forming an interlayer insulating layer on the sacrificial gate pattern, removing the sacrificial gate pattern to form a gap region exposing the active fin in the interlayer insulating layer, and oxidizing a portion of the active fin exposed by the gap region to form an insulation pattern between the active fin and the substrate.

公开(公告)号：US20140335673A1

公开(公告)日：2014-11-13

申请号：US14262937

申请日：2014-04-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： SUNGMIN KIM ,  Sung-Dae Suk ,  Jaehoo Park ,  Dongho Cha ,  Daewon Ha

IPC: H01L29/66

CPC classification number: H01L29/66795 ,  H01L21/02233 ,  H01L21/308 ,  H01L21/76224 ,  H01L21/845 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/6656

Abstract: A method of manufacturing a semiconductor device includes patterning a substrate to form an active fin, forming a sacrificial gate pattern crossing over the active fin on the substrate, forming an interlayer insulating layer on the sacrificial gate pattern, removing the sacrificial gate pattern to form a gap region exposing the active fin in the interlayer insulating layer, and oxidizing a portion of the active fin exposed by the gap region to form an insulation pattern between the active fin and the substrate.

Abstract translation: 制造半导体器件的方法包括：图案化衬底以形成有源鳍片，形成与衬底上的有源鳍片交叉的牺牲栅极图案，在牺牲栅极图案上形成层间绝缘层，去除牺牲栅极图案以形成 间隙区域使层间绝缘层中的活性鳍片曝光，并且氧化由间隙区域暴露的活性鳍片的一部分，以在活性鳍片和衬底之间形成绝缘图案。

公开(公告)号：US09276087B2

公开(公告)日：2016-03-01

申请号：US14262937

申请日：2014-04-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungmin Kim ,  Sung-Dae Suk ,  Jaehoo Park ,  Dongho Cha ,  Daewon Ha

IPC: H01L21/84 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L29/66795 ,  H01L21/02233 ,  H01L21/308 ,  H01L21/76224 ,  H01L21/845 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/6656

Abstract: A method of manufacturing a semiconductor device includes patterning a substrate to form an active fin, forming a sacrificial gate pattern crossing over the active fin on the substrate, forming an interlayer insulating layer on the sacrificial gate pattern, removing the sacrificial gate pattern to form a gap region exposing the active fin in the interlayer insulating layer, and oxidizing a portion of the active fin exposed by the gap region to form an insulation pattern between the active fin and the substrate.

Abstract translation: 制造半导体器件的方法包括：图案化衬底以形成有源鳍片，形成与衬底上的有源鳍片交叉的牺牲栅极图案，在牺牲栅极图案上形成层间绝缘层，去除牺牲栅极图案以形成 间隙区域使层间绝缘层中的活性鳍片曝光，并且氧化由间隙区域暴露的活性鳍片的一部分，以在活性鳍片和衬底之间形成绝缘图案。

公开(公告)号：US20150028399A1

公开(公告)日：2015-01-29

申请号：US14308751

申请日：2014-06-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junjie Xiong ,  Dongho Cha ,  Myung Jin Kang ,  Kihoon Do

IPC: H01L29/417

CPC classification number: H01L29/45 ,  H01L21/02532 ,  H01L21/76805 ,  H01L21/76895 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/41725 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7848

Abstract: Provided are semiconductor devices and methods of manufacturing the same. The methods include providing a substrate including a first region and a second region, forming first mask patterns in the first region, and forming second mask patterns having an etch selectivity with respect to the first mask patterns in the second region. The first mask patterns and the second mask patterns are formed at the same time.

Abstract translation: 提供半导体器件及其制造方法。 所述方法包括提供包括第一区域和第二区域的衬底，在第一区域中形成第一掩模图案，以及形成相对于第二区域中的第一掩模图案具有蚀刻选择性的第二掩模图案。 同时形成第一掩模图案和第二掩模图案。

公开(公告)号：US10439033B2

公开(公告)日：2019-10-08

申请号：US15350425

申请日：2016-11-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junjie Xiong ,  Dongho Cha ,  Myung Jin Kang ,  Kihoon Do

IPC: H01L29/45 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L29/165 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/768 ,  H01L27/092 ,  H01L29/08 ,  H01L29/16

Abstract: A semiconductor device can include a substrate with a first source/drain and a second source/drain in the substrate. A first ohmic contact pattern can be in an uppermost surface of the first source/drain, where the first ohmic contact pattern includes a first semiconductor alloyed with a first metal. A second ohmic contact pattern can be in an uppermost surface of the second source/drain, where the second ohmic contact pattern includes a second semiconductor that is different than the first semiconductor and is alloyed with a second metal that is different than the first metal.

公开(公告)号：US20170062579A1

公开(公告)日：2017-03-02

申请号：US15350425

申请日：2016-11-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junjie Xiong ,  Dongho Cha ,  Myung Jin Kang ,  Kihoon Do

IPC: H01L29/45 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L21/02 ,  H01L21/8238 ,  H01L21/285 ,  H01L21/768 ,  H01L21/762 ,  H01L29/66 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L29/45 ,  H01L21/02532 ,  H01L21/76805 ,  H01L21/76895 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/41725 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7848

Abstract: A semiconductor device can include a substrate with a first source/drain and a second source/drain in the substrate. A first ohmic contact pattern can be in an uppermost surface of the first source/drain, where the first ohmic contact pattern includes a first semiconductor alloyed with a first metal. A second ohmic contact pattern can be in an uppermost surface of the second source/drain, where the second ohmic contact pattern includes a second semiconductor that is different than the first semiconductor and is alloyed with a second metal that is different than the first metal.

Abstract translation: 半导体器件可以包括在衬底中具有第一源极/漏极和第二源极/漏极的衬底。 第一欧姆接触图案可以在第一源极/漏极的最上表面中，其中第一欧姆接触图案包括与第一金属合金化的第一半导体。 第二欧姆接触图案可以在第二源极/漏极的最上表面中，其中第二欧姆接触图案包括与第一半导体不同的第二半导体，并且与不同于第一金属的第二金属合金化。

公开(公告)号：US20140183599A1

公开(公告)日：2014-07-03

申请号：US14133064

申请日：2013-12-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soohun Hong ,  Heesoo Kang ,  Dongho Cha

IPC: H01L29/78

CPC classification number: H01L29/785 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/7848

Abstract: Field effect transistors are provided. An active region protrudes from a substrate and a gate electrode is provided on the active region. Source/drain regions are provided at both sides of the active region under the gate electrode, respectively. A width of a lower portion of the gate electrode is greater than a width of an upper portion of the gate electrode.

Abstract translation: 提供场效应晶体管。 有源区域从衬底突出，并且栅极电极设置在有源区域上。 源极/漏极区分别设置在栅电极下方的有源区的两侧。 栅电极的下部的宽度大于栅电极的上部的宽度。

公开(公告)号：US10043873B2

公开(公告)日：2018-08-07

申请号：US15060174

申请日：2016-03-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyoung Hwan Yeo ,  Seonguk Park ,  Seungjae Lee ,  Doyoung Choi ,  Sunhom Steve Paak ,  Tae Eung Yoon ,  Dongho Cha ,  Ruiyi Chen

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L29/40 ,  H01L29/66 ,  H01L27/11 ,  H01L29/417 ,  H01L29/78

Abstract: Provided is a semiconductor device with a field effect transistor. The semiconductor device includes a substrate, an active pattern on the substrate, a gate electrode crossing the active pattern and a capping structure on the gate electrode. The capping structure includes first and second capping patterns that are sequentially stacked on the gate electrode. The second capping pattern completely covers a top surface of the first capping pattern, and a dielectric constant of the second capping pattern is greater than that of the first capping pattern.

公开(公告)号：US09515150B2

公开(公告)日：2016-12-06

申请号：US14308751

申请日：2014-06-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junjie Xiong ,  Dongho Cha ,  Myung Jin Kang ,  Kihoon Do

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L29/165 ,  H01L21/8238

CPC classification number: H01L29/45 ,  H01L21/02532 ,  H01L21/76805 ,  H01L21/76895 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/41725 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7848

Abstract: Provided are semiconductor devices and methods of manufacturing the same. The methods include providing a substrate including a first region and a second region, forming first mask patterns in the first region, and forming second mask patterns having an etch selectivity with respect to the first mask patterns in the second region. The first mask patterns and the second mask patterns are formed at the same time.

Abstract translation: 提供半导体器件及其制造方法。 所述方法包括提供包括第一区域和第二区域的衬底，在第一区域中形成第一掩模图案，以及形成相对于第二区域中的第一掩模图案具有蚀刻选择性的第二掩模图案。 同时形成第一掩模图案和第二掩模图案。

公开(公告)号：US09269813B2

公开(公告)日：2016-02-23

申请号：US14133064

申请日：2013-12-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soohun Hong ,  Heesoo Kang ,  Dongho Cha

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/165

CPC classification number: H01L29/785 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/7848

Abstract: Field effect transistors are provided. An active region protrudes from a substrate and a gate electrode is provided on the active region. Source/drain regions are provided at both sides of the active region under the gate electrode, respectively. A width of a lower portion of the gate electrode is greater than a width of an upper portion of the gate electrode.

Abstract translation: 提供场效应晶体管。 有源区域从衬底突出，并且栅极电极设置在有源区域上。 源极/漏极区分别设置在栅电极下方的有源区的两侧。 栅电极的下部的宽度大于栅电极的上部的宽度。