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    Memory device scrambling address
    1.
    发明授权
    Memory device scrambling address 有权

    公开(公告)号：US10957380B2

    公开(公告)日：2021-03-23

    申请号：US16369034

    申请日：2019-03-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyun-sung Shin ,  Dae-Jeong Kim ,  Ik-Joon Choi

    IPC: G11C11/40 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/406 ,  G06F3/06 ,  G11C17/18 ,  G11C17/16

    Abstract: According to an exemplary embodiment, a memory device may include a memory cell array that includes memory cells connected to word lines arranged in sequential order depending on a sequential change of a row address, a row decoder that, for each row address input to the row decoder, scrambles a first bit of the row address and a second bit of the row address depending on a selection signal, thereby forming a scrambled row address, decodes the scrambled row address, and selects a word line from the word lines based on the scrambled row address, and an anti-fuse array that includes an anti-fuse in which a logical value of the selection signal is programmed. A first word line and a second word line of the word lines may be adjacent to each other, and a difference between a first value of the row address corresponding to the first word line and a second value of the row address corresponding to the second word line may be a value corresponding to the first bit.

    Stacked memory device, a system including the same and an associated method
    4.
    发明授权
    Stacked memory device, a system including the same and an associated method 有权

    公开(公告)号：US11114139B2

    公开(公告)日：2021-09-07

    申请号：US17172328

    申请日：2021-02-10

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyun-Sung Shin ,  Ik-Joon Choi ,  So-Young Kim ,  Tae-Kyu Byun ,  Jae-Youn Youn

    IPC: G11C7/10 ,  G11C5/06 ,  G11C5/04 ,  G06F3/06 ,  G06F7/523 ,  G06F12/06 ,  G11C7/06 ,  G11C7/22

    Abstract: A stacked memory device includes: a logic semiconductor die; a plurality of memory semiconductor dies stacked with the logic semiconductor die, wherein each of the memory semiconductor dies includes a memory integrated circuit and one or more of the memory semiconductor dies is a calculation semiconductor die including a calculation unit; and through-silicon vias electrically connecting the logic semiconductor die and the plurality of memory semiconductor dies, wherein each of the calculation units is configured to perform calculations based on broadcast data and internal data and to generate calculation result data, wherein the broadcast data is commonly provided to the calculation semiconductor dies through the through-silicon vias, and the internal data is respectively read from the memory integrated circuits of the calculation semiconductor dies.

    Stacked memory device, a system including the same and an associated method
    6.
    发明授权
    Stacked memory device, a system including the same and an associated method 有权

    公开(公告)号：US10923165B2

    公开(公告)日：2021-02-16

    申请号：US16743051

    申请日：2020-01-15

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyun-Sung Shin ,  Ik-Joon Choi ,  So-Young Kim ,  Tae-Kyu Byun ,  Jae-Youn Youn

    IPC: G11C7/10 ,  G11C5/06 ,  G11C5/04 ,  G06F3/06 ,  G06F7/523 ,  G06F12/06 ,  G11C7/06 ,  G11C7/22

    Abstract: A stacked memory device includes: a logic semiconductor die; a plurality of memory semiconductor dies stacked with the logic semiconductor die, wherein each of the memory semiconductor dies includes a memory integrated circuit and one or more of the memory semiconductor dies is a calculation semiconductor die including a calculation unit; and through-silicon vias electrically connecting the logic semiconductor die and the plurality of memory semiconductor dies, wherein each of the calculation units is configured to perform calculations based on broadcast data and internal data and to generate calculation result data, wherein the broadcast data is commonly provided to the calculation semiconductor dies through the through-silicon vias, and the internal data is respectively read from the memory integrated circuits of the calculation semiconductor dies.

    Stacked memory device, a system including the same and an associated method
    7.
    发明授权
    Stacked memory device, a system including the same and an associated method 有权

    公开(公告)号：US10553260B2

    公开(公告)日：2020-02-04

    申请号：US16038269

    申请日：2018-07-18

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyun-Sung Shin ,  Ik-Joon Choi ,  So-Young Kim ,  Tae-Kyu Byun ,  Jae-Youn Youn

    IPC: G11C7/10 ,  G06F3/06 ,  G06F7/523 ,  G06F12/06 ,  G11C7/06 ,  G11C7/22

    Abstract: A stacked memory device includes; a logic semiconductor die; a plurality of memory semiconductor dies stacked with the logic semiconductor die, wherein each of the memory semiconductor dies includes a memory integrated circuit and one or more of the memory semiconductor dies is a calculation semiconductor die including a calculation unit; and through-silicon vias electrically connecting the logic semiconductor die and the plurality of memory semiconductor dies, wherein each of the calculation units is configured to perform calculations based on broadcast data and internal data and to generate calculation result data, wherein the broadcast data is commonly provided to the calculation semiconductor dies through the through-silicon vias, and the internal data is respectively read from the memory integrated circuits of the calculation semiconductor dies.

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