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    EUV photomask and method of forming mask pattern using the same
    2.
    发明授权
    EUV photomask and method of forming mask pattern using the same 有权

    公开(公告)号：US11733601B2

    公开(公告)日：2023-08-22

    申请号：US17308484

    申请日：2021-05-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Soonmok Ha ,  Jaehee Kim ,  Sangho Yun ,  Chan Hwang

    IPC: G03F1/24

    CPC classification number: G03F1/24

    Abstract: An EUV photomask having a main area and a scribe lane area and reflecting EUV light includes a reflective multilayer film and an absorption pattern, wherein the scribe lane area includes first and second lanes, wherein the first lane includes first and second sub-lanes extending in the same direction as an extending direction of the first lane, wherein the first sub-lane includes a first dummy pattern that is a portion of the absorption pattern, and the second sub-lane includes a second dummy pattern that is a portion of the absorption pattern, and when EUV light that is not absorbed by the first and second dummy patterns and is reflected by the reflective multilayer film is irradiated at least twice by overlapping a negative tone photoresist, an amount of light exceeds a threshold dose of light in the negative tone photoresist corresponding to the first lane.

    METHODS OF FORMING FINE PATTERNS FOR SEMICONDUCTOR DEVICES
    3.
    发明申请
    METHODS OF FORMING FINE PATTERNS FOR SEMICONDUCTOR DEVICES 有权
    形成半导体器件精细图案的方法

    公开(公告)号：US20150104946A1

    公开(公告)日：2015-04-16

    申请号：US14467400

    申请日：2014-08-25

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： JOONSOO PARK ,  Soonmok Ha ,  Eunshoo Han ,  Seongho Moon ,  Sung-Wook Hwang

    IPC: H01L21/306 ,  H01L21/311 ,  H01L21/308

    CPC classification number: H01L21/30604 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31111 ,  H01L21/31144 ,  H01L27/10852 ,  H01L27/11551 ,  H01L27/11578

    Abstract: Methods of forming fine patterns for semiconductor devices are provided. A method may include sequentially forming a lower layer and a mask layer having first openings on a substrate, forming pillars to fill the first openings and protrude upward from a top surface of the mask layer, forming a block copolymer layer on the substrate with the pillars, performing a thermal treatment to the block copolymer layer to form a first block portion and second block portions, removing the second block portions to form guide openings exposing the mask layer, and etching the mask layer exposed by the guide openings to form second openings.

    Abstract translation: 提供了形成用于半导体器件的精细图案的方法。 一种方法可以包括顺序地形成下层和在衬底上具有第一开口的掩模层，形成柱以填充第一开口并从掩模层的顶表面向上突出，在衬底上形成具有柱的嵌段共聚物层 对所述嵌段共聚物层进行热处理以形成第一嵌段部分和第二嵌段部分，除去所述第二嵌段部分以形成暴露所述掩模层的引导开口，以及蚀刻由所述引导开口露出的掩模层以形成第二开口。

    SEMICONDUCTOR DEVICES AND METHODS FOR MANUFACTURING THE SAME
    6.
    发明申请
    SEMICONDUCTOR DEVICES AND METHODS FOR MANUFACTURING THE SAME 有权

    公开(公告)号：US20170103987A1

    公开(公告)日：2017-04-13

    申请号：US15237709

    申请日：2016-08-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jaehee Kim ,  Soonmok Ha ,  Jonghyuk Kim ,  Joonsoo Park

    IPC: H01L27/108

    CPC classification number: H01L27/10894 ,  H01L27/10814 ,  H01L27/10826 ,  H01L27/10852 ,  H01L27/10855 ,  H01L27/10879 ,  H01L27/10885 ,  H01L28/90

    Abstract: A method for manufacturing a semiconductor device includes forming first and second lower structures including selection elements on first and second chip regions of a substrate, respectively, forming first and second mold layers on the first and second lower structures, respectively, forming first and second support layers on the first and second mold layers, respectively, patterning the first support layer and the first mold layer to form first holes exposing the first lower structure, forming first lower electrodes in the first holes, forming a support pattern including at least one opening by selectively patterning the first support layer while leaving the second support layer, and removing the first mold layer through the opening. A top surface of the support pattern is disposed at a substantially same level as a top surface of the second support layer.

    Methods of forming fine patterns for semiconductor devices
    7.
    发明授权
    Methods of forming fine patterns for semiconductor devices 有权
    形成半导体器件精细图案的方法

    公开(公告)号：US09099399B2

    公开(公告)日：2015-08-04

    申请号：US14467400

    申请日：2014-08-25

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Joonsoo Park ,  Soonmok Ha ,  Eunshoo Han ,  Seongho Moon ,  Sung-Wook Hwang

    IPC: H01L21/02 ,  H01L21/306 ,  H01L21/308 ,  H01L21/311

    CPC classification number: H01L21/30604 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31111 ,  H01L21/31144 ,  H01L27/10852 ,  H01L27/11551 ,  H01L27/11578

    Abstract: Methods of forming fine patterns for semiconductor devices are provided. A method may include sequentially forming a lower layer and a mask layer having first openings on a substrate, forming pillars to fill the first openings and protrude upward from a top surface of the mask layer, forming a block copolymer layer on the substrate with the pillars, performing a thermal treatment to the block copolymer layer to form a first block portion and second block portions, removing the second block portions to form guide openings exposing the mask layer, and etching the mask layer exposed by the guide openings to form second openings.

    Abstract translation: 提供了形成用于半导体器件的精细图案的方法。 一种方法可以包括顺序地形成下层和在衬底上具有第一开口的掩模层，形成柱以填充第一开口并从掩模层的顶表面向上突出，在衬底上形成具有柱的嵌段共聚物层 对所述嵌段共聚物层进行热处理以形成第一嵌段部分和第二嵌段部分，除去所述第二嵌段部分以形成暴露所述掩模层的引导开口，以及蚀刻由所述引导开口露出的掩模层以形成第二开口。

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