公开(公告)号：US20240258396A1

公开(公告)日：2024-08-01

申请号：US18458438

申请日：2023-08-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun Ki PARK ,  Seon-Bae KIM ,  Sung Hwan KIM ,  Wan Don KIM ,  Jin Young PARK

IPC: H01L29/45 ,  H01L27/088 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/456 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/41775 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device may include gate structures spaced apart from each other on an active pattern, where each of the gate structures includes gate spacers on sidewalls of a gate electrode, source/drain patterns between the gate structures, source/drain contacts on the source/drain patterns, and contact silicide films between the source/drain contacts and the source/drain patterns. Outer surfaces of the contact silicide films may contact the source/drain patterns and inner surfaces of the contact silicide films may contact the source/drain contacts. A width in a first direction of the contact silicide films may be maximum at the uppermost portions of outer surfaces of the contact silicide films. Parts of the outer surfaces of the contact silicide films may contact the gate spacers. The width in the first direction of the uppermost portions of the contact silicide films may be equal to a width in the first direction of the source/drain contacts.

公开(公告)号：US20200013897A1

公开(公告)日：2020-01-09

申请号：US16451787

申请日：2019-06-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JONG HO PARK ,  Wan Don KIM ,  Weon Hong KIM ,  Hyeon Jun BAEK ,  Byoung Hoon LEE ,  Jeong Hyuk YIM ,  Sang Jin HYUN

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/51 ,  H01L29/49

Abstract: A semiconductor device including: a first transistor which include a first gate stack on a substrate; and a second transistor which includes a second gate stack on the substrate, wherein the first gate stack includes a first ferroelectric material layer disposed on the substrate, a first work function layer disposed on the first ferroelectric material layer and a first upper gate electrode disposed on the first work function layer, wherein the second gate stack. includes a second ferroelectric material layer disposed on the substrate, a second work function layer disposed on the second ferroelectric material layer and a second upper gate electrode disposed on the second work function layer, wherein the first work function layer includes the same material as the second work function layer, and wherein an effective work function of the first gate stack is different from an effective work function of the second gate stack.

公开(公告)号：US20240154042A1

公开(公告)日：2024-05-09

申请号：US18353276

申请日：2023-07-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun Ki PARK ,  Wan Don KIM ,  Jeong Hyuk YIM ,  Hyo Seok CHOI ,  Sung Hwan KIM

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423

CPC classification number: H01L29/78696 ,  H01L29/0673 ,  H01L29/41791 ,  H01L29/42392

Abstract: A semiconductor device includes a substrate including an upper surface and a lower surface that are opposite to each other in a first direction, an active pattern which is on the upper surface of the substrate and extends in a second direction, a gate electrode which is on the active pattern and extends in a third direction, a first source/drain pattern which is connected to the active pattern on the upper surface of the substrate, and includes a lower epitaxial region and an upper epitaxial region, the upper epitaxial region including an epitaxial recess, and the lower epitaxial region being inside the epitaxial recess, a first source/drain contact, which is connected to the first source/drain pattern and extends into the substrate, and a contact silicide layer, which is between the first source/drain contact and the first source/drain pattern and contacts the lower epitaxial region.

公开(公告)号：US20190355825A1

公开(公告)日：2019-11-21

申请号：US16214537

申请日：2018-12-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeong Hyuk YIM ,  Kug Hwan KIM ,  Wan Don KIM ,  Jung Min PARK ,  Jong Ho PARK ,  Byoung Hoon LEE ,  Yong Ho HA ,  Sang Jin HYUN ,  Hye Ri HONG

IPC: H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/49 ,  H01L29/78 ,  H01L27/092

Abstract: A semiconductor device according to an example embodiment of the present inventive concept includes a substrate having a first region and a second region horizontally separate from the first region; a first gate line in the first region, the first gate line including a first lower work function layer and a first upper work function layer disposed on the first lower work function layer; and a second gate line including a second lower work function layer in the second region, the second gate line having a width in a first, horizontal direction equal to or narrower than a width of the first gate line in the first direction, wherein an uppermost end of the first upper work function layer and an uppermost end of the second lower work function layer are each located at a vertical level higher than an uppermost end of the first lower work function layer with respect to a second direction perpendicular to the first direction.

公开(公告)号：US20240120279A1

公开(公告)日：2024-04-11

申请号：US18471730

申请日：2023-09-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeong Hyuk YIM ,  Wan Don KIM ,  Hyun Bae LEE ,  Hyo Seok CHOI ,  Geun Woo KIM

IPC: H01L23/535 ,  H01L21/768 ,  H01L23/528 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775

CPC classification number: H01L23/535 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76895 ,  H01L23/5286 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/775

Abstract: A semiconductor device may include a first film and a second film defining parts of a trench, a plug conductive film, a via, and a wiring in the trench. The trench may include a second sub-trench having a second width below a first sub-trench having a first width. The plug conductive film may extend from a first side of the first film to penetrate a bottom face of the trench. An uppermost face of the plug conducive film may be in the trench. The via may include an insulating liner between the plug conductive film and the first film. The uppermost face of the plug conductive film and at least a part of a side wall of the plug conductive film may be in contact with the wiring. An upper face of the insulating liner may be exposed by a bottom face of the second sub-trench.

公开(公告)号：US20240063276A1

公开(公告)日：2024-02-22

申请号：US18380754

申请日：2023-10-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heon Bok LEE ,  Dae Yong KIM ,  Wan Don KIM ,  Jeong Hyuk YIM ,  Won Keun CHUNG ,  Hyo Seok CHOI ,  Sang Jin HYUN

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/08 ,  H01L21/768 ,  H01L29/78

CPC classification number: H01L29/41775 ,  H01L29/6681 ,  H01L29/0847 ,  H01L21/76897 ,  H01L29/41791 ,  H01L29/7851

Abstract: A semiconductor device includes an active pattern on a substrate, the active pattern extending in a first direction, a gate electrode on the active pattern, the gate electrode extending in a second direction intersecting the first direction and including a first portion and a second portion arranged along the second direction, a first contact plug on the gate electrode, the first contact plug being connected to a top surface of the second portion of the gate electrode, a source/drain region in the active pattern on a sidewall of the gate electrode, and a source/drain contact on the source/drain region, a height of a top surface of the source/drain contact being higher than a top surface of the first portion of the gate electrode and lower than the top surface of the second portion of the gate electrode.

公开(公告)号：US20220165861A1

公开(公告)日：2022-05-26

申请号：US17669859

申请日：2022-02-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byoung Hoon LEE ,  Wan Don KIM ,  Jong Ho PARK ,  Sang Jin HYUN

IPC: H01L29/51 ,  H01L29/786 ,  H01L29/49 ,  H01L29/775 ,  H01L29/423

Abstract: A semiconductor device is provided. The semiconductor device comprising a multi-channel active pattern on a substrate, a high dielectric constant insulating layer formed along the multi-channel active pattern on the multi-channel active pattern, wherein the high dielectric constant insulating layer comprises a metal, a silicon nitride layer formed along the high dielectric constant insulating layer on the high dielectric constant insulating layer and a gate electrode on the silicon nitride layer.

公开(公告)号：US20220084952A1

公开(公告)日：2022-03-17

申请号：US17379000

申请日：2021-07-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jang Eun LEE ,  Min Joo LEE ,  Wan Don KIM ,  Hyeon Jin SHIN ,  Hyun Bae LEE ,  Hyun Seok LIM

IPC: H01L23/532

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate including an element isolation layer, the element isolation layer defining an active region, a plurality of word lines traversing the active region in a first direction, and a plurality of bit line structures on the substrate and connected to the active region, the plurality of bit line structures extending in a second direction different from the first direction. Each of the plurality of bit line structures includes a ruthenium line wiring including a bottom surface and a top surface opposite to the bottom surface, a lower graphene layer in contact with the bottom surface of the ruthenium line wiring and extending along the bottom surface of the ruthenium line wiring, and a wiring line capping layer extending along the top surface of the ruthenium line wiring.

公开(公告)号：US20250063763A1

公开(公告)日：2025-02-20

申请号：US18441269

申请日：2024-02-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Won Keun CHUNG ,  Geun Woo KIM ,  Jun Ki PARK ,  Wan Don KIM ,  Hyo Seok CHOI

IPC: H01L29/417 ,  H01L21/285 ,  H01L23/528 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor device may include a backside wiring line in a first backside interlayer insulating film, a fin-type pattern on the backside wiring line, a second backside interlayer insulating film between the fin-type pattern and the first backside interlayer insulating film, a gate electrode on the fin-type pattern, a first source/drain pattern on a side of the gate electrode, and a backside source/drain contact in a backside contact hole defined by the fin-type pattern and the second backside interlayer insulating film. The backside source/drain contact may connect the backside wiring line and the first source/drain pattern. The backside source/drain contact may include an upper pattern and a lower pattern. The upper pattern may be between the lower pattern and the first source/drain pattern, and may fill at least a portion of the first backside contact hole. The upper pattern may have a single conductive film structure.

公开(公告)号：US20250029897A1

公开(公告)日：2025-01-23

申请号：US18634372

申请日：2024-04-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jun Ki PARK ,  Sung Hwan KIM ,  Wan Don KIM ,  Won Keun CHUNG

IPC: H01L23/485 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor device includes a back interlayer insulating film, a back wiring line in the back interlayer insulating film, the back wiring line including a first surface and a second surface opposite the first surface in a first direction, a fin-type pattern on the first surface of the back wiring line and extending in a second direction, a gate electrode on the fin-type pattern and extending in a third direction, a first source/drain pattern on a first side of the gate electrode, the first source/drain pattern including a bottom surface contacting the fin-type pattern, a back source/drain contact in the fin-type pattern and connected to the first surface of the back wiring line, and a contact insulating liner between the fin-type pattern and the back source/drain contact, the contact insulating liner extending along at least a portion of side walls of the back source/drain contact.