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公开(公告)号:US20220285518A1
公开(公告)日:2022-09-08
申请号:US17826380
申请日:2022-05-27
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Nam Gyu CHO , Rak Hwan KIM , Hyeok-Jun SON , Do Sun LEE , Won Keun CHUNG
IPC: H01L29/49 , H01L29/06 , H01L29/423 , H01L29/66 , H01L21/28 , H01L21/311 , H01L29/786
Abstract: A semiconductor device and a method of fabricating a semiconductor device, the device including a fin-type pattern extending in a first direction; a gate electrode extending in a second direction over the fin-type pattern, the second direction being different from the first direction; spacers on sidewalls of the gate electrode; a capping structure on the gate electrode and the spacers, the capping structure including a first capping pattern and a second capping pattern, the second capping pattern being on the first capping pattern; and an interlayer insulating film surrounding sidewalls of each of the spacers and sidewalls of the capping structure, the interlayer insulating film being in contact with the first capping pattern.
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公开(公告)号:US20210210613A1
公开(公告)日:2021-07-08
申请号:US17015296
申请日:2020-09-09
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Nam Gyu CHO , Rak Hwan KIM , Hyeok-Jun SON , Do Sun LEE , Won Keun CHUNG
IPC: H01L29/49 , H01L29/06 , H01L29/423 , H01L29/786 , H01L21/28 , H01L21/311 , H01L29/66
Abstract: A semiconductor device and a method of fabricating a semiconductor device, the device including a fin-type pattern extending in a first direction; a gate electrode extending in a second direction over the fin-type pattern, the second direction being different from the first direction; spacers on sidewalls of the gate electrode; a capping structure on the gate electrode and the spacers, the capping structure including a first capping pattern and a second capping pattern, the second capping pattern being on the first capping pattern; and an interlayer insulating film surrounding sidewalls of each of the spacers and sidewalls of the capping structure, the interlayer insulating film being in contact with the first capping pattern.
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公开(公告)号:US20240128347A1
公开(公告)日:2024-04-18
申请号:US18397700
申请日:2023-12-27
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Nam Gyu CHO , Rak Hwan KIM , Hyeok-Jun SON , Do Sun LEE , Won Keun CHUNG
IPC: H01L29/49 , H01L21/28 , H01L21/311 , H01L29/06 , H01L29/423 , H01L29/66 , H01L29/786
CPC classification number: H01L29/4983 , H01L21/28132 , H01L21/31111 , H01L29/0673 , H01L29/42392 , H01L29/4908 , H01L29/6653 , H01L29/66553 , H01L29/66742 , H01L29/78696
Abstract: A semiconductor device and a method of fabricating a semiconductor device, the device including a fin-type pattern extending in a first direction; a gate electrode extending in a second direction over the fin-type pattern, the second direction being different from the first direction; spacers on sidewalls of the gate electrode; a capping structure on the gate electrode and the spacers, the capping structure including a first capping pattern and a second capping pattern, the second capping pattern being on the first capping pattern; and an interlayer insulating film surrounding sidewalls of each of the spacers and sidewalls of the capping structure, the interlayer insulating film being in contact with the first capping pattern.
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公开(公告)号:US20220199790A1
公开(公告)日:2022-06-23
申请号:US17694759
申请日:2022-03-15
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Heon Bok LEE , Dae Yong KIM , Wan Don Kim , Jeong Hyuk YIM , Won Keun CHUNG , Hyo Seok CHOI , Sang Jin HYUN
IPC: H01L29/417 , H01L29/66 , H01L29/08 , H01L21/768 , H01L29/78
Abstract: A semiconductor device includes an active pattern on a substrate, the active pattern extending in a first direction, a gate electrode on the active pattern, the gate electrode extending in a second direction intersecting the first direction and including a first portion and a second portion arranged along the second direction, a first contact plug on the gate electrode, the first contact plug being connected to a top surface of the second portion of the gate electrode, a source/drain region in the active pattern on a sidewall of the gate electrode, and a source/drain contact on the source/drain region, a height of a top surface of the source/drain contact being higher than a top surface of the first portion of the gate electrode and lower than the top surface of the second portion of the gate electrode.
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公开(公告)号:US20250063763A1
公开(公告)日:2025-02-20
申请号:US18441269
申请日:2024-02-14
Applicant: Samsung Electronics Co., Ltd.
Inventor: Won Keun CHUNG , Geun Woo KIM , Jun Ki PARK , Wan Don KIM , Hyo Seok CHOI
IPC: H01L29/417 , H01L21/285 , H01L23/528 , H01L29/06 , H01L29/40 , H01L29/423 , H01L29/45 , H01L29/66 , H01L29/775 , H01L29/786
Abstract: A semiconductor device may include a backside wiring line in a first backside interlayer insulating film, a fin-type pattern on the backside wiring line, a second backside interlayer insulating film between the fin-type pattern and the first backside interlayer insulating film, a gate electrode on the fin-type pattern, a first source/drain pattern on a side of the gate electrode, and a backside source/drain contact in a backside contact hole defined by the fin-type pattern and the second backside interlayer insulating film. The backside source/drain contact may connect the backside wiring line and the first source/drain pattern. The backside source/drain contact may include an upper pattern and a lower pattern. The upper pattern may be between the lower pattern and the first source/drain pattern, and may fill at least a portion of the first backside contact hole. The upper pattern may have a single conductive film structure.
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公开(公告)号:US20250029897A1
公开(公告)日:2025-01-23
申请号:US18634372
申请日:2024-04-12
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jun Ki PARK , Sung Hwan KIM , Wan Don KIM , Won Keun CHUNG
IPC: H01L23/485 , H01L29/06 , H01L29/08 , H01L29/423 , H01L29/66 , H01L29/775 , H01L29/786
Abstract: A semiconductor device includes a back interlayer insulating film, a back wiring line in the back interlayer insulating film, the back wiring line including a first surface and a second surface opposite the first surface in a first direction, a fin-type pattern on the first surface of the back wiring line and extending in a second direction, a gate electrode on the fin-type pattern and extending in a third direction, a first source/drain pattern on a first side of the gate electrode, the first source/drain pattern including a bottom surface contacting the fin-type pattern, a back source/drain contact in the fin-type pattern and connected to the first surface of the back wiring line, and a contact insulating liner between the fin-type pattern and the back source/drain contact, the contact insulating liner extending along at least a portion of side walls of the back source/drain contact.
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公开(公告)号:US20180350983A1
公开(公告)日:2018-12-06
申请号:US16100804
申请日:2018-08-10
Applicant: Samsung Electronics Co., Ltd.
Inventor: Won Keun CHUNG , Jong Ho PARK , Seung Ha OH , Sang Yong KIM , Hoon Joo NA , Sang Jin HYUN
IPC: H01L29/78 , H01L29/66 , H01L29/423 , H01L29/51 , H01L21/324 , H01L29/06 , H01L21/283
CPC classification number: H01L29/7831 , B82Y10/00 , H01L21/283 , H01L21/324 , H01L29/0653 , H01L29/0673 , H01L29/0676 , H01L29/42356 , H01L29/42364 , H01L29/42392 , H01L29/4908 , H01L29/511 , H01L29/513 , H01L29/66439 , H01L29/66484 , H01L29/66666 , H01L29/775 , H01L29/7827 , H01L29/78696
Abstract: A semiconductor device and a method for fabricating the same are provided. The semiconductor device includes first and second gate stack structures formed in first and second regions, respectively, wherein the first gate stack structure is formed adjacent a first channel region and comprises a first gate insulating film having a first thickness formed on the first channel region, a first function film having a second thickness formed on the first gate insulating film and a first filling film having a third thickness formed on the first function film, wherein the second gate stack structure is formed adjacent a second channel region and comprises a second gate insulating film having the first thickness formed on the second channel region, a second function film having the second thickness formed on the second gate insulating film and a second filling film having the third thickness formed on the second function film, wherein the first and second function films, respectively, comprise TiN and Si concentrations that are different from each other.
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公开(公告)号:US20240063276A1
公开(公告)日:2024-02-22
申请号:US18380754
申请日:2023-10-17
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Heon Bok LEE , Dae Yong KIM , Wan Don KIM , Jeong Hyuk YIM , Won Keun CHUNG , Hyo Seok CHOI , Sang Jin HYUN
IPC: H01L29/417 , H01L29/66 , H01L29/08 , H01L21/768 , H01L29/78
CPC classification number: H01L29/41775 , H01L29/6681 , H01L29/0847 , H01L21/76897 , H01L29/41791 , H01L29/7851
Abstract: A semiconductor device includes an active pattern on a substrate, the active pattern extending in a first direction, a gate electrode on the active pattern, the gate electrode extending in a second direction intersecting the first direction and including a first portion and a second portion arranged along the second direction, a first contact plug on the gate electrode, the first contact plug being connected to a top surface of the second portion of the gate electrode, a source/drain region in the active pattern on a sidewall of the gate electrode, and a source/drain contact on the source/drain region, a height of a top surface of the source/drain contact being higher than a top surface of the first portion of the gate electrode and lower than the top surface of the second portion of the gate electrode.
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公开(公告)号:US20220319916A1
公开(公告)日:2022-10-06
申请号:US17838740
申请日:2022-06-13
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Won Keun CHUNG , Joon Gon LEE , Rak Hwan KIM , Chung Hwan SHIN , Do Sun LEE , Nam Gyu CHO
IPC: H01L21/768
Abstract: A semiconductor device includes a first interlayer insulating film; a conductive connection structure provided in the first interlayer insulating film; a second interlayer insulating film provided on the first interlayer insulating film; a wiring structure provided in the second interlayer insulating film and connected to the conductive connection structure; and an insertion liner interposed between an upper surface of the conductive connection structure and the wiring structure, the insertion liner including carbon.
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公开(公告)号:US20180130905A1
公开(公告)日:2018-05-10
申请号:US15620631
申请日:2017-06-12
Applicant: Samsung Electronics Co., Ltd.
Inventor: Won Keun CHUNG , Jong Ho PARK , Seung Ha OH , Sang Yong KIM , Hoon Joo NA , Sang Jin HYUN
IPC: H01L29/78 , H01L29/66 , H01L29/51 , H01L29/06 , H01L29/423 , H01L21/324 , H01L21/283
CPC classification number: H01L29/7831 , B82Y10/00 , H01L21/283 , H01L21/324 , H01L29/0653 , H01L29/0673 , H01L29/0676 , H01L29/42356 , H01L29/42364 , H01L29/42392 , H01L29/4908 , H01L29/511 , H01L29/513 , H01L29/66439 , H01L29/66484 , H01L29/66666 , H01L29/775 , H01L29/7827 , H01L29/78696
Abstract: A semiconductor device and a method for fabricating the same are provided. The semiconductor device includes first and second gate stack structures formed in first and second regions, respectively, wherein the first gate stack structure is formed adjacent a first channel region and comprises a first gate insulating film having a first thickness formed on the first channel region, a first function film having a second thickness formed on the first gate insulating film and a first filling film having a third thickness formed on the first function film, wherein the second gate stack structure is formed adjacent a second channel region and comprises a second gate insulating film having the first thickness formed on the second channel region, a second function film having the second thickness formed on the second gate insulating film and a second filling film having the third thickness formed on the second function film, wherein the first and second function films, respectively, comprise TiN and Si concentrations that are different from each other.
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