DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE DISPLAY APPARATUS

    公开(公告)号:US20250089425A1

    公开(公告)日:2025-03-13

    申请号:US18883770

    申请日:2024-09-12

    Abstract: Provided is a display apparatus including a display substrate, a first pad and a second pad, a first electrode on the first pad, a multilayer semiconductor layer including a first-type semiconductor layer, an active layer, and a second-type semiconductor layer on the first electrode, an insulating layer on the display substrate and adjacent to the first pad, the first electrode, and the multilayer semiconductor layer, a height of the insulating layer being lower than an upper surface of the multilayer semiconductor layer, and a second electrode on an upper surface of the multilayer semiconductor layer, an exposed lateral surface of the multilayer semiconductor layer, and a surface of the insulating layer, the second electrode connecting the second-type semiconductor layer and the second pad, an angle between the exposed lateral surface of the multilayer semiconductor layer and an upper surface of the insulating layer is 90 degrees or more.

    Multi-qubit device and quantum computer including the same

    公开(公告)号:US09882112B2

    公开(公告)日:2018-01-30

    申请号:US15388668

    申请日:2016-12-22

    CPC classification number: H01L39/223 G06N99/002 H01L27/18

    Abstract: Multi-qubit devices and quantum computers including the same are provided. The multi-qubit device may include a first layer including a plurality of qubits; a second layer that is disposed on the first layer, and comprises a plurality of flux generating elements that apply flux to the plurality of qubits, a plurality of wire patterns that provide current to the plurality of flux generating elements, and a plurality of plugs that are disposed perpendicular to the plurality of flux generating elements and the plurality of wire patterns and interconnect the plurality of flux generating elements and the plurality of wire patterns. Each of the plurality of flux generating elements may be integrated with a corresponding one of the plurality of wire patterns and a corresponding one of the plurality of plugs.

    Vertical nonvolatile memory device including memory cell string

    公开(公告)号:US12272402B2

    公开(公告)日:2025-04-08

    申请号:US17708362

    申请日:2022-03-30

    Abstract: Provided is a vertical nonvolatile memory device in which a thickness of one memory cell is reduced to reduce an entire thickness of a memory cell string and increase the number of stacked memory cells. The nonvolatile memory device includes a plurality of memory cell strings. Each of the memory cell strings may include a plurality of insulating spacers each extending in a first direction, a plurality of gate electrodes each extending in the first direction and alternately arranged with the plurality of insulating spacers in a second direction perpendicular to the first direction, and a plurality of contacts respectively arranged to contact a side surface of the plurality of gate electrodes respectively corresponding to the plurality of contacts.

    Transistor including electride electrode

    公开(公告)号:US11799010B2

    公开(公告)日:2023-10-24

    申请号:US17227456

    申请日:2021-04-12

    CPC classification number: H01L29/45

    Abstract: Provided are transistors including an electride electrode. The transistor includes a substrate, a source region and a drain region doped with ions of different polarity from the substrate in a surface of the substrate, a source electrode and a drain electrode including an electride material on the source region and the drain region, a gate insulating layer surrounding the source electrode and a drain electrode on the substrate, and a gate electrode between the source electrode and the drain electrode on the substrate. The source electrode and the drain electrode have an ohmic contact with the substrate.

    Transistor including electride electrode

    公开(公告)号:US11004949B2

    公开(公告)日:2021-05-11

    申请号:US16238706

    申请日:2019-01-03

    Abstract: Provided are transistors including an electride electrode. The transistor includes a substrate, a source region and a drain region doped with ions of different polarity from the substrate in a surface of the substrate, a source electrode and a drain electrode including an electride material on the source region and the drain region, a gate insulating layer surrounding the source electrode and a drain electrode on the substrate, and a gate electrode between the source electrode and the drain electrode on the substrate. The source electrode and the drain electrode have an ohmic contact with the substrate.

    TRANSISTOR INCLUDING ELECTRIDE ELECTRODE
    9.
    发明申请

    公开(公告)号:US20200044041A1

    公开(公告)日:2020-02-06

    申请号:US16238706

    申请日:2019-01-03

    Abstract: Provided are transistors including an electride electrode. The transistor includes a substrate, a source region and a drain region doped with ions of different polarity from the substrate in a surface of the substrate, a source electrode and a drain electrode including an electride material on the source region and the drain region, a gate insulating layer surrounding the source electrode and a drain electrode on the substrate, and a gate electrode between the source electrode and the drain electrode on the substrate. The source electrode and the drain electrode have an ohmic contact with the substrate.

    Silicene electronic device
    10.
    发明授权

    公开(公告)号:US11245021B2

    公开(公告)日:2022-02-08

    申请号:US17028205

    申请日:2020-09-22

    Abstract: A silicene electronic device includes a silicene material layer. The silicene material layer of the silicene electronic device has a 2D honeycomb structure of silicon atoms, is doped with at least one material of Group I, Group II, Group XVI, and Group XVII, and includes at least one of a p-type dopant region doped with a p-type dopant and an n-type dopant region doped with an n-type dopant. An electrode material layer including a material having a work function lower than the electron affinity of silicene is formed on the silicene material layer.

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