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    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
    4.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权

    公开(公告)号：US20210217897A1

    公开(公告)日：2021-07-15

    申请号：US17004427

    申请日：2020-08-27

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Minhee CHO ,  Hyunmog Park ,  Minwoo Song ,  Woobin Song ,  Hyunsil Oh ,  Minsu Lee

    IPC: H01L29/786 ,  H01L27/12

    Abstract: A semiconductor device includes: a substrate including an active region and a device isolation region; a flat plate structure formed on the substrate; an oxide semiconductor layer covering a top surface of the flat plate structure and continuously arranged on a top surface of the substrate in the active region and the device isolation region; a gate structure arranged on the oxide semiconductor layer and including a gate dielectric layer and a gate electrode; and a source/drain region arranged on both sides of the gate structure and formed in the oxide semiconductor layer, in which, when viewed from a side cross-section, an extending direction of the flat plate structure and an extending direction of the gate structure cross each other.

    INTEGRATED CIRCUIT DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME
    7.
    发明公开
    INTEGRATED CIRCUIT DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME 审中-公开

    公开(公告)号：US20240107779A1

    公开(公告)日：2024-03-28

    申请号：US18467753

    申请日：2023-09-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyunmog Park

    IPC: H10B63/00

    CPC classification number: H10B63/84 ,  H10B63/82 ,  H10B80/00

    Abstract: An integrated circuit device includes a plurality of conductive lines extending on a semiconductor substrate in a horizontal direction and overlapping each other in a vertical direction, a plurality of insulating layers alternating with the plurality of conductive lines and extending in the horizontal direction, and a channel structure extending through the plurality of conductive lines and the plurality of insulating layers. The channel structure includes a core insulating layer, a resistance change layer on a side wall and a bottom surface of the core insulating layer, a channel layer on an outside wall of the resistance change layer, and a pad pattern on a top surface of the core insulating layer. A topmost surface of the resistance change layer is in contact with the core insulating layer and is spaced apart from a bottommost surface of the pad pattern.

    THREE-DIMENSIONAL MEMORY DEVICE INCLUDING A VARIABLE RESISTANCE MEMORY
    9.
    发明申请
    THREE-DIMENSIONAL MEMORY DEVICE INCLUDING A VARIABLE RESISTANCE MEMORY 有权

    公开(公告)号：US20220384524A1

    公开(公告)日：2022-12-01

    申请号：US17738366

    申请日：2022-05-06

    Applicant: SAMSUNG ELECTRONICS CO.,LTD.

    Inventor： Hyunmog Park ,  Jungyu Lee

    IPC: H01L27/24 ,  H01L45/00 ,  H01L23/528

    Abstract: A three-dimensional memory device includes: a plurality of word line groups including a plurality of word lines; a plurality of bit line groups extending in a vertical direction and including a plurality of bit lines spaced apart from the plurality of word lines; a plurality of memory cells arranged between the plurality of word lines and the plurality of bit lines and including a switching component and a variable resistance memory component; a plurality of global bit line groups connected to the plurality of bit line groups, wherein each of the plurality of global bit line groups includes a plurality of global bit lines electrically connected to a plurality of bit lines included in one bit line group, respectively; and a pad structure including a plurality of connection units and a plurality of pad layers, wherein the plurality of connection units are connected to the plurality of word line groups.

    SEMICONDUCTOR MEMORY DEVICE
    10.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20210257369A1

    公开(公告)日：2021-08-19

    申请号：US17313570

    申请日：2021-05-06

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Beomyong Hwang ,  Min Hee Cho ,  Hei Seung Kim ,  Mirco Cantoro ,  Hyunmog Park ,  Woo Bin Song ,  Sang Woo Lee

    IPC: H01L27/108 ,  G11C11/402

    Abstract: A semiconductor device includes a substrate, a peripheral circuit layer, a first active pattern, a gate electrode, a first insulating layer, a conductive contact, and a second active pattern. The peripheral circuit layer is disposed on the substrate, and the peripheral circuit layer includes logic transistors and an interconnection layer that is disposed on the logic transistors. The first active pattern is disposed on the peripheral circuit layer. The gate electrode is disposed on a channel region of the first active pattern. The first insulating layer is disposed on the first active pattern and the gate electrode. The conductive contact is disposed in the first insulating layer and is electrically connected to a first source/drain region of the first active pattern, and the second active pattern is disposed on the first insulating layer. The channel region of the second active pattern vertically overlaps with the conductive contact.

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