公开(公告)号：US20240201103A1

公开(公告)日：2024-06-20

申请号：US18220985

申请日：2023-07-12

Applicant: SAMSUNG ELECTRONICS CO., LTD

Inventor： Myunggeun SONG ,  Sarah KIM ,  Changyul KIM ,  Younghoon KIM ,  Jaeyong PARK ,  Sungil CHO ,  Taeil CHO

IPC: G01N21/94

CPC classification number: G01N21/94 ,  G01N2201/1248

Abstract: An inspection method includes extracting a first similarity by comparing first data of a first optical signal with reference data of a reference optical signal, generating a first normal distribution of the first similarity, extracting a second similarity by comparing second data of a second optical signal with the reference data of the reference optical signal, generating a second normal distribution of the second similarity, and comparing the first normal distribution with the second normal distribution. The extracting of the first similarity includes deriving the first data of the first optical signal.

公开(公告)号：US20230065995A1

公开(公告)日：2023-03-02

申请号：US17591949

申请日：2022-02-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Inchul SONG ,  Hyuk KIM ,  Sangwuk PARK ,  Jun Haeng LEE ,  Sungil CHO ,  Kaeweon YOU

IPC: G06F16/904

Abstract: A processor-implemented method with data exploration includes: setting first input data and a first target condition; predicting first output data corresponding to the first input data using a first function that models an objective function; and determining second input data using a second function that provides a result of comparison between the first output data and the first target condition.

公开(公告)号：US20220293622A1

公开(公告)日：2022-09-15

申请号：US17668824

申请日：2022-02-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Choasub KIM ,  Bongtae PARK ,  Jae-Joo SHIM ,  Sungil CHO

IPC: H01L27/11565 ,  H01L23/535 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11573

Abstract: A semiconductor device may include a first cell block including a first electrode structure including first electrodes stacked on a substrate, and first channels penetrating the first electrode structure, and a second cell block including a second electrode structure including second electrodes stacked on the substrate, and second channels penetrating the second electrode structure. The first and second electrode structures may extend in a first direction. The first electrode structure may have a first width in a second direction, and the second electrode structure may have a second width greater than the first width. A side surface of the first electrode structure and the first channel adjacent thereto may be apart from each other by a first distance, and a side surface of the second electrode structure and the second channel adjacent thereto may be apart from each other by a second distance different from the first distance.

公开(公告)号：US20170358540A1

公开(公告)日：2017-12-14

申请号：US15622708

申请日：2017-06-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byoung-Gug MIN ,  Sungil CHO ,  Jaehoon CHOI ,  Shi-kyung KIM

IPC: H01L23/552

CPC classification number: H01L23/552 ,  H01L21/561 ,  H01L23/295 ,  H01L23/3128 ,  H01L23/3135 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/1815 ,  H01L2924/3025 ,  H01L2224/81

Abstract: Semiconductor packages and a methods for manufacturing a semiconductor package are provided. The method includes providing a package including a substrate, a semiconductor chip provided on the substrate, and a molding layer provided on the substrate and covering the semiconductor chip, the substrate including a ground pattern exposed at one surface of the substrate; and applying a solution including metal particles and a conductive carbon material onto the molding layer to form a shielding layer covering the molding layer. The shielding layer includes the metal particles and the conductive carbon material connected to at least one of the metal particles. The shielding layer extends onto the one surface of the substrate and is electrically connected to the ground pattern.

公开(公告)号：US20240071732A1

公开(公告)日：2024-02-29

申请号：US18236748

申请日：2023-08-22

Applicant: SAMSUNG ELECTRONICS CO.,LTD.

Inventor： Hyun-Sik HWANG ,  Jinyoung BANG ,  Sungil CHO ,  Junghwan UM

IPC: H01J37/32 ,  H01L21/3065 ,  H01L21/311

CPC classification number: H01J37/32642 ,  H01J37/32449 ,  H01J37/32724 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/31144 ,  H01J2237/334

Abstract: A dry etching apparatus includes a process chamber; a support provided in the process chamber and configured to support a substrate; a gas supply configured to supply a process gas including a hydrogen gas (H2) and a fluorocarbon gas (CxFy) into the process chamber; a plasma source configured to generate plasma using the process gas in the process chamber, wherein the support includes: an electrostatic chuck on which the substrate is disposed; an edge ring provided along a circumference of the electrostatic chuck and supporting an edge region of the substrate; an adhesive gel pad provided between the electrostatic chuck and the edge ring; and a coating layer formed only on a surface of the edge ring, which is exposed to the plasma.

公开(公告)号：US20190157237A1

公开(公告)日：2019-05-23

申请号：US16057323

申请日：2018-08-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yong Je LEE ,  Seunglo LEE ,  Sungil CHO ,  Hosoo HAN

IPC: H01L23/00

Abstract: A semiconductor device includes a first device having a first pad; a second device having a second pad; and a bonding wire electrically connecting the first device and the second device to each other via the first pad and the second pad. The bonding wire includes: a first bonding structure provided at a first end of the bonding wire, electrically connected to the first device and includes: a first ball bonding region; and a first stitch bonding region; and a second bonding structure provided at a second end opposite of the first end of the bonding wire and electrically connected to the second device.

公开(公告)号：US20160104618A1

公开(公告)日：2016-04-14

申请号：US14715631

申请日：2015-05-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Sil HONG ,  Sungil CHO

IPC: H01L21/033 ,  H01L21/311 ,  H01L27/108 ,  H01L49/02 ,  H01L21/02 ,  H01L21/31 ,  H01L21/283

CPC classification number: H01L21/0332 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0334 ,  H01L21/31 ,  H01L21/31116 ,  H01L21/31144 ,  H01L27/10852 ,  H01L28/90

Abstract: A method of manufacturing a semiconductor device is provided. The method includes forming a molding layer and a supporter layer on a semiconductor substrate, forming a multiple mask layer including a first mask layer and a second mask layer formed on the first mask layer, on the supporter layer. The first mask layer is formed of a material having an etch selectivity with respect to the molding layer and the second mask layer is formed of a material having an etch selectivity with respect to the supporter layer. The method includes forming a first mask pattern and a second mask pattern formed on the first mask pattern by patterning the multiple mask layer, etching the supporter layer by performing a first etching process using the second mask pattern as an etch mask, etching the molding layer, and forming a hole by performing a second etching process using the first mask pattern as an etch mask.

Abstract translation: 提供一种制造半导体器件的方法。 该方法包括在半导体衬底上形成模制层和支撑层，在支撑层上形成包括形成在第一掩模层上的第一掩模层和第二掩模层的多掩模层。 第一掩模层由相对于模制层具有蚀刻选择性的材料形成，并且第二掩模层由相对于载体层具有蚀刻选择性的材料形成。 该方法包括通过对多个掩模层进行构图来形成形成在第一掩模图案上的第一掩模图案和第二掩模图案，通过使用第二掩模图案作为蚀刻掩模进行第一蚀刻工艺来蚀刻支撑层，蚀刻成型层 并且通过使用第一掩模图案作为蚀刻掩模执行第二蚀刻工艺来形成孔。