公开(公告)号：US11495280B2

公开(公告)日：2022-11-08

申请号：US17399349

申请日：2021-08-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeongseok Seo ,  Kwanghyun Kim ,  Chikook Kim ,  Seungwoo Ryu ,  Doohee Hwang

IPC: G11C11/40 ,  G11C11/4072 ,  H01L25/065

Abstract: A semiconductor memory device includes an external resistor provided on a board and a plurality of memory dies mounted on the board, designated as a master die and slave dies. The memory dies are commonly connected to the external resistor. The master die performs a first impedance calibration operation during an initialization sequence of the semiconductor memory device and stores, in a first register set therein, first calibration data, a first voltage and a first temperature. Each of the slave dies, after the first impedance calibration operation is completed, performs a second impedance calibration operation during the initialization sequence and stores, in a second register set therein, second calibration data associated with the second impedance calibration operation and offset data corresponding to a difference between the first calibration data and the second calibration data.

公开(公告)号：US20240144988A1

公开(公告)日：2024-05-02

申请号：US18213826

申请日：2023-06-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeongseok Seo ,  Chulhwan Choo ,  Doohee Hwang

IPC: G11C11/406 ,  G06F3/06 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4096

CPC classification number: G11C11/406 ,  G06F3/0619 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/0673 ,  G11C11/4087 ,  G11C11/4091 ,  G11C11/4096

Abstract: A method of operating a memory device, the method includes periodically receiving a refresh command from a host, determining whether a target row address is activated during a predetermined period of time, and skipping a refresh operation on a word line corresponding to the target row address when the target row address is activated, and transmitting, to the host, a refresh skip signal corresponding to the word line on which the refresh operation is skipped, or performing, in response to the refresh command, a refresh operation on a word line corresponding to the target row address when the target row address is not activated.

公开(公告)号：US11508429B2

公开(公告)日：2022-11-22

申请号：US17399402

申请日：2021-08-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeonkyu Choi ,  Dokyun Kim ,  Seongjin Lee ,  Doohee Hwang

IPC: G11C11/406 ,  G11C7/10

Abstract: A memory system includes a memory controller and a memory device. The memory controller generates refresh commands periodically by an average refresh interval. The memory device performs a normal refresh operation and a hammer refresh operation during a refresh cycle time. The memory device includes a memory cell array including memory cells connected to a plurality of wordlines, a temperature sensor configured to provide temperature information by measuring an operation temperature of the memory cell array and a refresh controller configured to control the normal refresh operation and the hammer refresh operation. The refresh controller varies a hammer ratio of a unit hammer execution number of the hammer refresh operation executed during the refresh cycle time with respect to a unit normal execution number of the normal refresh operation executed during the refresh cycle time.

公开(公告)号：US20220278273A1

公开(公告)日：2022-09-01

申请号：US17749289

申请日：2022-05-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YUKIO HAYAKAWA ,  Jooheon Kang ,  Myunghun Woo ,  Gunwook Yoon ,  Doohee Hwang

IPC: H01L45/00 ,  H01L27/24 ,  G11C13/00

Abstract: A vertical variable resistance memory device includes gate electrodes and a pillar structure. The gate electrodes are spaced apart from one another on a substrate in a vertical direction substantially perpendicular to an upper surface of the substrate. The pillar structure extends in the vertical direction through the gate electrodes on the substrate. The pillar structure includes a vertical gate electrode extending in the vertical direction, a variable resistance pattern disposed on a sidewall of the vertical gate electrode, and a channel disposed on an outer sidewall of the variable resistance pattern. The channel and the vertical gate electrode contact each other.

公开(公告)号：US20250040176A1

公开(公告)日：2025-01-30

申请号：US18629093

申请日：2024-04-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngtaek Oh ,  Jiwoong Kim ,  Taehun Kim ,  Minkyung Bae ,  Seungjae Baik ,  Jaeduk Lee ,  Doohee Hwang

IPC: H01L29/78 ,  H01L23/00 ,  H01L25/065 ,  H01L29/08 ,  H01L29/10 ,  H10B80/00

Abstract: A semiconductor device includes a peripheral circuit structure and a cell structure stacked on the peripheral circuit structure. The cell structure includes a plurality of gate electrodes spaced apart from each other in a vertical direction, a channel structure passing through the plurality of gate electrodes and extending in the vertical direction, the channel structure having a first end close to the peripheral circuit structure and a second end opposite to the first end, and a common source layer covering the second end of the channel structure. The channel structure includes a channel layer extending in the vertical direction, the common source layer includes a first region and a second region that contain impurities of different conductivity types, and the first region of the common source layer is connected to at least a portion of the channel layer.

公开(公告)号：US11957071B2

公开(公告)日：2024-04-09

申请号：US17749289

申请日：2022-05-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yukio Hayakawa ,  Jooheon Kang ,  Myunghun Woo ,  Gunwook Yoon ,  Doohee Hwang

IPC: G11C13/00 ,  H10B63/00 ,  H10N70/00

CPC classification number: H10N70/826 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0038 ,  G11C13/0069 ,  H10B63/34 ,  H10N70/841 ,  H10N70/8833

Abstract: A vertical variable resistance memory device includes gate electrodes and a pillar structure. The gate electrodes are spaced apart from one another on a substrate in a vertical direction substantially perpendicular to an upper surface of the substrate. The pillar structure extends in the vertical direction through the gate electrodes on the substrate. The pillar structure includes a vertical gate electrode extending in the vertical direction, a variable resistance pattern disposed on a sidewall of the vertical gate electrode, and a channel disposed on an outer sidewall of the variable resistance pattern. The channel and the vertical gate electrode contact each other.

公开(公告)号：US11778825B2

公开(公告)日：2023-10-03

申请号：US17702967

申请日：2022-03-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bongyong Lee ,  Taehun Kim ,  Minkyung Bae ,  Myunghun Woo ,  Doohee Hwang

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/35 ,  H10B43/40

CPC classification number: H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/35 ,  H10B43/40

Abstract: A vertical semiconductor layer includes a common source semiconductor layer on a substrate, a support layer on the common source semiconductor layer, gates and interlayer insulating layers alternately stacked on the support layer, a channel pattern extending in a first direction perpendicular to an upper surface of the substrate while penetrating the gates and the support layer, a sidewall of the support layer facing the channel pattern being offset relative to sidewalls of the gates facing the channel pattern, and an information storage layer extending between the gates and the channel pattern, the information storage layer extending at least to the sidewall of the support layer facing the channel pattern.

公开(公告)号：US11315946B2

公开(公告)日：2022-04-26

申请号：US16838106

申请日：2020-04-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bongyong Lee ,  Taehun Kim ,  Minkyung Bae ,  Myunghun Woo ,  Doohee Hwang

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11524

Abstract: A vertical semiconductor layer includes a common source semiconductor layer on a substrate, a support layer on the common source semiconductor layer, gates and interlayer insulating layers alternately stacked on the support layer, a channel pattern extending in a first direction perpendicular to an upper surface of the substrate while penetrating the gates and the support layer, a sidewall of the support layer facing the channel pattern being offset relative to sidewalls of the gates facing the channel pattern, and an information storage layer extending between the gates and the channel pattern, the information storage layer extending at least to the sidewall of the support layer facing the channel pattern.

公开(公告)号：US20240161807A1

公开(公告)日：2024-05-16

申请号：US18234157

申请日：2023-08-15

Applicant: SAMSUNG ELECTRONICS CO. LTD.

Inventor： Junha HWANG ,  Youngbin lee ,  Kangil Kim ,  Saemi Song ,  Kiseok Oh ,  Doohee Hwang

IPC: G11C11/406 ,  G11C29/52

CPC classification number: G11C11/40622 ,  G11C11/40615 ,  G11C29/52

Abstract: A memory device is provided. The memory device includes: a memory cell array including a plurality of memory cell rows; a refresh control circuit configured to output a refresh row address to control a refresh operation to be performed on at least one memory cell row among the plurality of memory cell rows; and a control logic circuit configured to receive, from a memory controller, error check and scrub (ECS) setting data corresponding to a mode among a plurality of modes, store the ECS setting data in a mode register, and provide a target row address of a memory cell row to be refreshed to the refresh control circuit based on a value of the ECS setting data in response to a refresh command provided from the memory controller.

公开(公告)号：US11804254B2

公开(公告)日：2023-10-31

申请号：US17529900

申请日：2021-11-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Saemi Song ,  Dokyun Kim ,  Yeonkyu Choi ,  Doohee Hwang

IPC: G11C11/406

CPC classification number: G11C11/40626 ,  G11C11/40615 ,  G11C11/40622

Abstract: Provided are a memory device and a method of refreshing the memory device regardless of a refresh rate multiplier for a temperature. In response to a refresh command at each base refresh rate (tREFi) based on a measured temperature, a memory device refreshes M memory cell rows at room temperature, refreshes 2M memory cell rows at a high temperature, and refreshes (½)M memory cell rows at a low temperature. The memory device refreshes (n+1)*M memory cell rows at a base refresh rate tREFi in response to a refresh command applied after n skipped base refresh rates, and refreshes (n+1)*M memory cell rows at a base refresh rate tREFi in response to a pulling-in refresh command.