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公开(公告)号：US20190294372A1
公开(公告)日：2019-09-26
申请号：US16184328
申请日：2018-11-08
Applicant: SK hynix Inc.
Inventor： Hyun Woo LEE
Abstract: A memory controller includes an interleaving component configured to determine an access sequence of a plurality of memory units based on estimated execution times for the respective memory units to perform an operation, and a processor configured to access the memory units in the determined access sequence to perform the operation in an interleaved manner.
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2.发明申请SEMICONDUCTOR MEMORY APPARATUS AND OPERATING METHOD OF SEMICONDUCTOR SYSTEM USING THE SAME 审中-公开使用其的半导体系统的半导体存储器件和操作方法公开(公告)号：US20160232957A1
公开(公告)日：2016-08-11
申请号：US14729528
申请日：2015-06-03
Applicant: SK hynix Inc.
Inventor： Soo Young JANG , Hyun Woo LEE
CPC classification number: G06F12/02 , G11C7/08 , G11C7/12 , G11C8/06 , G11C8/08 , G11C8/10 , G11C8/12 , G11C8/18
Abstract: A semiconductor memory apparatus includes an address determination block configured to output an address as one of a row address and a column address according to an internal command; a row address decoding block configured to decode the row address and enable a word line; a column address decoding block configured to decode a partial column address of the column address and enable a column select signal; a data select signal generation block configured to enable a data select signal according to the row address and a remaining column address of the column address; and a data storage region configured to store or output data according to the word line, the column select signal and the data select signal.
Abstract translation: 半导体存储装置包括地址确定块，被配置为根据内部命令将地址作为行地址和列地址之一输出; 行地址解码块，被配置为对行地址进行解码并使能字线; 列地址解码块，被配置为对列地址的部分列地址进行解码并使能列选择信号; 数据选择信号生成块，被配置为根据行地址和列地址的剩余列地址启用数据选择信号; 以及数据存储区域，被配置为根据字线，列选择信号和数据选择信号来存储或输出数据。
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公开(公告)号：US20210311830A1
公开(公告)日：2021-10-07
申请号：US17006062
申请日：2020-08-28
Applicant: SK hynix Inc.
Inventor： Hyun Woo LEE
Abstract: The present technology relates to an electronic device. According to the present technology, a storage device having improved original data recovery capability may include a memory device including a plurality of memory cells, and configured to perform a read operation on data stored in the plurality of memory cells according to read mode information, and to output read data associated with the read operation and a memory controller configured to receive the read data, change the read mode information when error correction decoding for the read data fails, and control the memory device to perform the read operation again according to the changed read mode information. The read mode information may include information on a data interface between the memory device and the memory controller.
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公开(公告)号：US20210011650A1
公开(公告)日：2021-01-14
申请号：US16667396
申请日：2019-10-29
Applicant: SK hynix Inc.
Inventor： Hyun Woo LEE
IPC: G06F3/06
Abstract: A controller, a memory system and an operating method thereof are disclosed. The operating method of a controller includes controlling a nonvolatile memory device to perform a first erase operation on invalidated memory blocks; allocating a target memory block for a write operation among the memory blocks on which the first erase operation is performed; controlling the nonvolatile memory device to perform an erase state verifying operation on the target memory block; and controlling the nonvolatile memory device to perform the write operation on the target memory block when the erase state verifying operation indicates that an erase state of the target memory block satisfies a set condition.
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公开(公告)号：US20200057580A1
公开(公告)日：2020-02-20
申请号：US16298604
申请日：2019-03-11
Applicant: SK hynix Inc.
Inventor： Young Gyun KIM , Hyun Woo LEE
Abstract: A semiconductor memory device includes a memory cell array, a peripheral circuit, a control logic, and a temperature sensor. The memory cell array includes a plurality of memory cells. The peripheral circuit performs an operation on the memory cell array. The control logic controls an operation of the peripheral circuit, and generates a ready-busy signal representing whether the operation of the peripheral circuit is completed. The temperature sensor measures a temperature of the semiconductor memory device. The control logic generates the ready-busy signal, based on the temperature.
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Patent Agency Ranking
公开(公告)号：US20150155869A1
公开(公告)日：2015-06-04
申请号：US14190372
申请日：2014-02-26
Applicant: SK hynix Inc.
Inventor： Hyun Woo LEE
IPC: H03K19/00 , H03K3/356 , H03K19/094 , H03K3/012
CPC classification number: H03K19/0008 , H03K3/012 , H03K3/356034 , H03K19/0013 , H03K19/08 , H03K19/09436
Abstract: A semiconductor apparatus may include a mode control circuit configured to output differential output signals which swing in a current mode logic (CML) area and a first control signal, in response to a power-down mode signal; a first circuit unit configured to be provided with the differential output signals, and operate in a power-down mode; and a second circuit unit configured to be provided with the differential output signals, and be interrupted in its operation in the power-down mode.
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公开(公告)号：US20200042245A1
公开(公告)日：2020-02-06
申请号：US16299272
申请日：2019-03-12
Applicant: SK hynix Inc.
Inventor： Hyun Woo LEE , Young Gyun KIM
Abstract: A memory system includes a memory device and a memory controller. The memory device includes a plurality of memory cells. The memory controller controls the memory device to perform a plurality of read operations on memory cells included in a selected physical page among the plurality of memory cells. The memory controller calculates an inverted bit number representing different bit values, based on a plurality of read data received from the memory device. The memory controller performs a read reclaim operation on the selected physical page, based on the inverted bit number.
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公开(公告)号：US20190129782A1
公开(公告)日：2019-05-02
申请号：US16231882
申请日：2018-12-24
Applicant: SK hynix Inc.
Inventor： Hyun Woo LEE
Abstract: An electronic system includes a memory controller and a memory. The memory controller generates a plurality of controller clocks having different phases from one another based on a reference clock signal. The memory generates a plurality of internal clocks having different phases from one another by receiving first and second clocks having a phase difference from each other, and outputs one of odd-ordered data and even-ordered data in synchronization with the plurality of internal clocks.
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9.发明申请公开(公告)号：US20150364176A1
公开(公告)日：2015-12-17
申请号：US14476340
申请日：2014-09-03
Applicant: SK hynix Inc.
Inventor： Hyun Woo LEE
CPC classification number: G06F11/079 , G11C7/222 , G11C29/022 , G11C29/023 , G11C29/028
Abstract: An electronic system includes a memory controller and a memory. The memory controller generates a plurality of controller clocks having different phases from one another based on a reference clock signal. The memory generates a plurality of internal clocks having different phases from one another by receiving first and second clocks having a phase difference from each other, and outputs one of odd-ordered data and even-ordered data in synchronization with the plurality of internal clocks.
Abstract translation: 电子系统包括存储器控制器和存储器。 存储器控制器基于参考时钟信号产生具有彼此不同相位的多个控制器时钟。 存储器通过接收彼此具有相位差的第一和第二时钟来产生彼此具有不同相位的多个内部时钟，并且与多个内部时钟同步地输出奇数有序数据和偶数序数据之一。
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公开(公告)号：US20200225859A1
公开(公告)日：2020-07-16
申请号：US16549437
申请日：2019-08-23
Applicant: SK hynix Inc.
Inventor： Hyun Woo LEE , Young Gyun KIM
IPC: G06F3/06
Abstract: A storage device having an improved operation speed includes a memory controller for controlling a memory device. The memory controller includes a parameter data generator for generating parameter data for changing a parameter value related to an operation of the memory device, and a parameter controller for outputting the parameter data. The parameter data includes an error protection field associated with the parameter value.
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