公开(公告)号：US20170344278A1

公开(公告)日：2017-11-30

申请号：US15493289

申请日：2017-04-21

Applicant: SK hynix Inc.

Inventor： Do-Sun HONG ,  Jung Hyun KWON ,  Donggun KIM ,  Yong Ju KIM ,  Sungeun LEE ,  Jae Sun LEE ,  Sang Gu JO ,  JINGZHE XU

IPC: G06F3/06 ,  G06F12/10

CPC classification number: G06F3/0616 ,  G06F3/0632 ,  G06F3/0653 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0246 ,  G06F12/10 ,  G06F2212/1041 ,  G06F2212/65 ,  G06F2212/7205 ,  G11C13/0033 ,  G11C13/0035 ,  G11C16/349

Abstract: A memory controller may be provided. The memory controller may include a wear-leveler may be configured to determine whether execution of a swapping operation is required based on reception of a write command for a stack region.

公开(公告)号：US20180060166A1

公开(公告)日：2018-03-01

申请号：US15611151

申请日：2017-06-01

Applicant: SK hynix Inc.

Inventor： Sungeun LEE ,  Jung Hyun KWON ,  Yong Ju KIM ,  Jae Sun LEE ,  JINGZHE XU

IPC: G06F11/10 ,  H03M13/19 ,  H03M13/15 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G06F11/1012 ,  G11C29/52 ,  G11C2029/0411 ,  H03M13/152 ,  H03M13/19

Abstract: A semiconductor system includes a host and a media controller. The host may generate first host parities from first host data based on an error check matrix. The media controller may include a first input/output (I/O) circuit and a second I/O circuit. The media controller may generate first media data and first media parities based on the first host data and the first host parities. The first I/O circuit may generate, based on the error check matrix, first internal data by correcting errors in the first host data using the first host parities. The second I/O circuit may generate the first media data and the first media parities from the first internal data.

公开(公告)号：US20180052732A1

公开(公告)日：2018-02-22

申请号：US15469047

申请日：2017-03-24

Applicant: SK hynix Inc.

Inventor： Sang Gu JO ,  Jung Hyun KWON ,  Donggun KIM ,  Yong Ju KIM ,  Sungeun LEE ,  Jae Sun LEE ,  JINGZHE XU ,  Do-Sun HONG

IPC: G06F11/10 ,  G11C29/52

CPC classification number: G06F11/1048 ,  G11C29/52 ,  G11C2029/0401

Abstract: A semiconductor system may be provided. The semiconductor system may include a first semiconductor device configured for outputting a transmission command and a transmission address, being inputted with and outputting transmission data, and generating an error flag signal when an error bit is included in the transmission data inputted in a read operation. The semiconductor system may include a second semiconductor device configured for storing the transmission address in a lookup table circuit when the error flag signal is enabled, and comparing the transmission address and a storage address stored in the lookup table circuit when the read operation is performed based on the transmission command and outputting the transmission data from the lookup table circuit.

公开(公告)号：US20180019007A1

公开(公告)日：2018-01-18

申请号：US15492182

申请日：2017-04-20

Applicant: SK hynix Inc.

Inventor： Sung Eun LEE ,  Jung Hyun KWON ,  Jae Sun LEE ,  JINGZHE XU

IPC: G11C7/10 ,  G06F13/16 ,  G11C11/406

CPC classification number: G11C7/1072 ,  G06F13/1663 ,  G06F13/1673 ,  G06F13/1684 ,  G11C7/10 ,  G11C7/1075 ,  G11C11/40607

Abstract: A data processing system may include a memory/storage circuit and a host. The memory/storage circuit may include a first memory module and a second memory module. Each of the first and second memory modules may include a controller and a memory device. The host may have access to the memory device of the first memory module and the memory device of the second memory module. Each of the controllers included in the first and second memory modules may be configured to selectively perform any one of a memory operation and a storage operation according to a request of the host.

公开(公告)号：US20170344422A1

公开(公告)日：2017-11-30

申请号：US15377024

申请日：2016-12-13

Applicant: SK hynix Inc.

Inventor： Jung Hyun KWON ,  JINGZHE XU ,  Do Sun HONG

IPC: G06F11/10 ,  G06F3/06 ,  G11C29/52

CPC classification number: G06F3/0673 ,  G06F3/0619 ,  G06F3/064 ,  G06F11/1048 ,  G11C29/52 ,  G11C2029/0411

Abstract: A semiconductor device may be provided. The semiconductor device may include an error correction circuit and a verification operation control circuit. The error correction circuit may be configured to output first correction data obtained by correcting an error of first read data inputted through a transmission data signal received, externally from the error correction circuit, as a correction data signal and configured to generate a write control signal according to the number of errors of the first read data. The verification operation control circuit may be configured to receive first correction data through the correction data signal to output the first correction data through an internal correction data signal and configured to generate an internal command signal for storing the first correction data externally from the semiconductor device, based on the write control signal.