公开(公告)号：US20210019227A1

公开(公告)日：2021-01-21

申请号：US16883783

申请日：2020-05-26

申请人： SK hynix Inc.

发明人： Won Gyu SHIN ,  Jung Hyun KWON ,  Jin Woong SUH ,  Do Sun HONG

IPC分类号： G06F11/10 ,  H03M13/15

摘要： A memory system includes a memory medium, a loop-buffer configured to store read data outputted from the memory medium in a first operation mode, a fake-command generator configured to generate a fake-command in a second operation mode, and an error correction code (ECC) decoder configured to perform an ECC decoding operation of the read data stored in the loop-buffer in response to the fake-command.

公开(公告)号：US20180261298A1

公开(公告)日：2018-09-13

申请号：US15821155

申请日：2017-11-22

申请人： SK hynix Inc.

发明人： Donggun KIM ,  Yong Ju KIM ,  Do Sun HONG

IPC分类号： G11C29/38 ,  G06F3/06 ,  G11C29/36

摘要： A nonvolatile memory system may include a nonvolatile memory device, a delegate page attacker, and a health status analyzer. The nonvolatile memory device may include at least one memory block including a plurality of storage pages and a delegate page. The delegate page attacker may be configured to attack a bit of the delegate page at the same corresponding location as a bit of the storage page in which an error occurs. The health status analyzer may be configured to perform write and read operations for the delegate page and analyzes error information occurred in the write and read operations to determine whether the nonvolatile memory device is in a failure status.

公开(公告)号：US20190303253A1

公开(公告)日：2019-10-03

申请号：US16212302

申请日：2018-12-06

申请人： SK hynix Inc.

发明人： Wongyu SHIN ,  Jung Hyun KWON ,  Seunggyu JEONG ,  Do Sun HONG

IPC分类号： G06F11/20 ,  G06F11/10 ,  G11C29/52

摘要： A semiconductor memory system includes a memory medium and a data input/output (I/O) pin repair control circuit. The memory medium includes a plurality of memory dies and a spare die. Each of the plurality of memory dies has a plurality of memory regions and a plurality of data I/O pins, and the spare die has a plurality of spare regions and a plurality of data I/O pins. The data I/O pin repair control circuit performs a repair process for replacing an abnormal data I/O pin among the plurality of data I/O pins included in any of the plurality of memory dies with a data I/O pin of the plurality of data I/O pins included in the spare die.

公开(公告)号：US20180308542A1

公开(公告)日：2018-10-25

申请号：US15822718

申请日：2017-11-27

申请人： SK hynix Inc.

发明人： Donggun KIM ,  Jung Hyun KWON ,  Yong Ju KIM ,  Do Sun HONG

IPC分类号： G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/08 ,  G11C7/10 ,  G06F12/02

CPC分类号： G11C11/5628 ,  G06F12/0246 ,  G11C7/1006 ,  G11C7/12 ,  G11C8/08 ,  G11C11/5642 ,  G11C13/0023 ,  G11C13/0069 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/3427

摘要： An address distribution apparatus includes an address distributor. The address distributor distributes addresses of a plurality of memory cells in a memory device to prevent at least two successive write operations from being applied to at least two adjacent memory cells sharing any one of a plurality of word lines or any one of a plurality of bit lines among the plurality of memory cells. The at least two write operations are performed in response to write requests outputted from a host, respectively.

公开(公告)号：US20170329389A1

公开(公告)日：2017-11-16

申请号：US15230734

申请日：2016-08-08

申请人： SK hynix Inc.

发明人： Yong Ju KIM ,  Jung Hyun KWON ,  Donggun KIM ,  Sungeun LEE ,  Jae Sun LEE ,  Sang Gu JO ,  Jingzhe XU ,  Do Sun HONG

IPC分类号： G06F1/32 ,  G11C11/4074 ,  G11C11/406 ,  G06F12/121 ,  G06F12/1009 ,  G11C11/4091 ,  G06F12/02

CPC分类号： G06F1/3287 ,  G06F1/3275 ,  G06F12/0223 ,  G06F12/1009 ,  G06F12/121 ,  G11C11/40615 ,  G11C11/4074 ,  G11C11/4091 ,  G11C2207/2227

摘要： In an embodiment of the present disclosure, a memory module may be provided. In an embodiment of the present disclosure, a system may be provided. In an embodiment of the present disclosure, an operation of a system and memory module may be provided. The memory module may include a plurality of ranks in which a defragmentation operation of a memory is performed based on entrance of a low-power operation mode, and a vacant region of the memory is powered off based on entrance of a self-refresh mode after the defragmentation operation is ended. The memory module may include a page table of which data are updated based on an ending of the defragmentation operation of the memory.

公开(公告)号：US20210286674A1

公开(公告)日：2021-09-16

申请号：US17332448

申请日：2021-05-27

申请人： SK hynix Inc.

发明人： Won Gyu SHIN ,  Jung Hyun KWON ,  Jin Woong SUH ,  Do Sun HONG

IPC分类号： G06F11/10 ,  H03M13/15

摘要： An error correction method may include performing a first error correction code (ECC) decoding operation of read data outputted from a memory medium and storing the read data outputted from the memory medium into a loop-buffer, in a first operation mode, and performing a second ECC decoding operation of the read data stored in the loop-buffer may be performed in a second operation mode.

公开(公告)号：US20190267055A1

公开(公告)日：2019-08-29

申请号：US16210303

申请日：2018-12-05

申请人： SK hynix Inc.

发明人： Seunggyu JEONG ,  Jung Hyun KWON ,  Wongyu SHIN ,  Do Sun HONG

IPC分类号： G11C7/22 ,  G11C16/32 ,  G11C16/26 ,  G11C7/10 ,  G06F9/30 ,  G06F11/07 ,  G06F11/30

摘要： A read time-out manager may include a counter and a plurality of timers. The counter may generate a counter output signal based on a first cycle time. The plurality of timers may be each configured to be assigned a read identification to measure a time-out period corresponding to the read identification. Each of the plurality of timers may operate in synchronization with the counter output signal to generate a time-out signal based on a second cycle time different from the first cycle time.

公开(公告)号：US20190171561A1

公开(公告)日：2019-06-06

申请号：US16271431

申请日：2019-02-08

申请人： SK hynix Inc.

发明人： Donggun KIM ,  Yong Ju KIM ,  Do Sun HONG

IPC分类号： G06F12/02

摘要： A memory apparatus and a method of wear-leveling of a memory apparatus may be provided. The memory apparatus may include a memory having a plurality of storage blocks and a plurality of free blocks. The memory apparatus may include a memory controller configured for performing a first global wear-leveling to move data of a first storage block, which is a hot block among the storage blocks, to a first free block among the free blocks. The memory apparatus may include a memory controller configured for remapping a result of a logic operation of a logical page address of each of the pages in the first storage block and a first security refresh key to a physical page address of each of the pages in the first free block.

公开(公告)号：US20170344422A1

公开(公告)日：2017-11-30

申请号：US15377024

申请日：2016-12-13

申请人： SK hynix Inc.

发明人： Jung Hyun KWON ,  JINGZHE XU ,  Do Sun HONG

IPC分类号： G06F11/10 ,  G06F3/06 ,  G11C29/52

CPC分类号： G06F3/0673 ,  G06F3/0619 ,  G06F3/064 ,  G06F11/1048 ,  G11C29/52 ,  G11C2029/0411

摘要： A semiconductor device may be provided. The semiconductor device may include an error correction circuit and a verification operation control circuit. The error correction circuit may be configured to output first correction data obtained by correcting an error of first read data inputted through a transmission data signal received, externally from the error correction circuit, as a correction data signal and configured to generate a write control signal according to the number of errors of the first read data. The verification operation control circuit may be configured to receive first correction data through the correction data signal to output the first correction data through an internal correction data signal and configured to generate an internal command signal for storing the first correction data externally from the semiconductor device, based on the write control signal.