公开(公告)号：US20180052732A1

公开(公告)日：2018-02-22

申请号：US15469047

申请日：2017-03-24

Applicant: SK hynix Inc.

Inventor： Sang Gu JO ,  Jung Hyun KWON ,  Donggun KIM ,  Yong Ju KIM ,  Sungeun LEE ,  Jae Sun LEE ,  JINGZHE XU ,  Do-Sun HONG

IPC: G06F11/10 ,  G11C29/52

CPC classification number: G06F11/1048 ,  G11C29/52 ,  G11C2029/0401

Abstract: A semiconductor system may be provided. The semiconductor system may include a first semiconductor device configured for outputting a transmission command and a transmission address, being inputted with and outputting transmission data, and generating an error flag signal when an error bit is included in the transmission data inputted in a read operation. The semiconductor system may include a second semiconductor device configured for storing the transmission address in a lookup table circuit when the error flag signal is enabled, and comparing the transmission address and a storage address stored in the lookup table circuit when the read operation is performed based on the transmission command and outputting the transmission data from the lookup table circuit.

公开(公告)号：US20180019007A1

公开(公告)日：2018-01-18

申请号：US15492182

申请日：2017-04-20

Applicant: SK hynix Inc.

Inventor： Sung Eun LEE ,  Jung Hyun KWON ,  Jae Sun LEE ,  JINGZHE XU

IPC: G11C7/10 ,  G06F13/16 ,  G11C11/406

CPC classification number: G11C7/1072 ,  G06F13/1663 ,  G06F13/1673 ,  G06F13/1684 ,  G11C7/10 ,  G11C7/1075 ,  G11C11/40607

Abstract: A data processing system may include a memory/storage circuit and a host. The memory/storage circuit may include a first memory module and a second memory module. Each of the first and second memory modules may include a controller and a memory device. The host may have access to the memory device of the first memory module and the memory device of the second memory module. Each of the controllers included in the first and second memory modules may be configured to selectively perform any one of a memory operation and a storage operation according to a request of the host.

公开(公告)号：US20160292090A1

公开(公告)日：2016-10-06

申请号：US14725003

申请日：2015-05-29

Applicant: SK hynix Inc.

Inventor： Yong Ju KIM ,  Sang Gu JO ,  Jae Sun LEE

IPC: G06F13/10 ,  G06F13/12

CPC classification number: G06F13/102 ,  G06F13/12

Abstract: A data processing system includes a plurality of peripheral devices in which device identification information and group identification information are stored, and a controller. The peripheral devices of the same species device group have the same group identification information, and peripheral devices from different peripheral device groups have different group identification information. The controller controls peripheral devices of the same species device group to perform the same operation.

Abstract translation: 数据处理系统包括存储设备识别信息和组识别信息的多个外围设备和控制器。 同一种类设备组的外围设备具有相同的组识别信息，来自不同外设设备组的外围设备具有不同的组识别信息。 控制器控制同一物种设备组的外围设备执行相同的操作。

公开(公告)号：US20180060166A1

公开(公告)日：2018-03-01

申请号：US15611151

申请日：2017-06-01

Applicant: SK hynix Inc.

Inventor： Sungeun LEE ,  Jung Hyun KWON ,  Yong Ju KIM ,  Jae Sun LEE ,  JINGZHE XU

IPC: G06F11/10 ,  H03M13/19 ,  H03M13/15 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G06F11/1012 ,  G11C29/52 ,  G11C2029/0411 ,  H03M13/152 ,  H03M13/19

Abstract: A semiconductor system includes a host and a media controller. The host may generate first host parities from first host data based on an error check matrix. The media controller may include a first input/output (I/O) circuit and a second I/O circuit. The media controller may generate first media data and first media parities based on the first host data and the first host parities. The first I/O circuit may generate, based on the error check matrix, first internal data by correcting errors in the first host data using the first host parities. The second I/O circuit may generate the first media data and the first media parities from the first internal data.

公开(公告)号：US20170329389A1

公开(公告)日：2017-11-16

申请号：US15230734

申请日：2016-08-08

Applicant: SK hynix Inc.

Inventor： Yong Ju KIM ,  Jung Hyun KWON ,  Donggun KIM ,  Sungeun LEE ,  Jae Sun LEE ,  Sang Gu JO ,  Jingzhe XU ,  Do Sun HONG

IPC: G06F1/32 ,  G11C11/4074 ,  G11C11/406 ,  G06F12/121 ,  G06F12/1009 ,  G11C11/4091 ,  G06F12/02

CPC classification number: G06F1/3287 ,  G06F1/3275 ,  G06F12/0223 ,  G06F12/1009 ,  G06F12/121 ,  G11C11/40615 ,  G11C11/4074 ,  G11C11/4091 ,  G11C2207/2227

Abstract: In an embodiment of the present disclosure, a memory module may be provided. In an embodiment of the present disclosure, a system may be provided. In an embodiment of the present disclosure, an operation of a system and memory module may be provided. The memory module may include a plurality of ranks in which a defragmentation operation of a memory is performed based on entrance of a low-power operation mode, and a vacant region of the memory is powered off based on entrance of a self-refresh mode after the defragmentation operation is ended. The memory module may include a page table of which data are updated based on an ending of the defragmentation operation of the memory.

公开(公告)号：US20180011754A1

公开(公告)日：2018-01-11

申请号：US15434314

申请日：2017-02-16

Applicant: SK hynix Inc.

Inventor： Jung Hyun KWON ,  Sung Eun LEE ,  Jae Sun LEE ,  Jingzhe XU

IPC: G06F11/07 ,  G06F3/06

CPC classification number: G06F11/0727 ,  G06F11/0793 ,  G06F11/1048

Abstract: A memory system may be provided. The memory system may include a memory apparatus including a plurality of memory cells. The memory system may include and a controller configured to control a write operation and a read operation with respect to the memory apparatus, detect an error occurrence position by performing the write operation and the read operation on a corresponding region of the memory apparatus in which an error occurs based on error occurrence address information generated in the read operation while changing a level of data to be written, and determine a type of error based on the detected error occurrence position.

公开(公告)号：US20170344278A1

公开(公告)日：2017-11-30

申请号：US15493289

申请日：2017-04-21

Applicant: SK hynix Inc.

Inventor： Do-Sun HONG ,  Jung Hyun KWON ,  Donggun KIM ,  Yong Ju KIM ,  Sungeun LEE ,  Jae Sun LEE ,  Sang Gu JO ,  JINGZHE XU

IPC: G06F3/06 ,  G06F12/10

CPC classification number: G06F3/0616 ,  G06F3/0632 ,  G06F3/0653 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0246 ,  G06F12/10 ,  G06F2212/1041 ,  G06F2212/65 ,  G06F2212/7205 ,  G11C13/0033 ,  G11C13/0035 ,  G11C16/349

Abstract: A memory controller may be provided. The memory controller may include a wear-leveler may be configured to determine whether execution of a swapping operation is required based on reception of a write command for a stack region.