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11 条记录 (耗时 0.016 秒)

    MEMORY SYSTEM INCLUDING A DELEGATE PAGE AND METHOD OF IDENTIFYING A STATUS OF A MEMORY SYSTEM
    1.
    发明申请
    MEMORY SYSTEM INCLUDING A DELEGATE PAGE AND METHOD OF IDENTIFYING A STATUS OF A MEMORY SYSTEM 审中-公开

    公开(公告)号：US20180261298A1

    公开(公告)日：2018-09-13

    申请号：US15821155

    申请日：2017-11-22

    申请人： SK hynix Inc.

    发明人： Donggun KIM ,  Yong Ju KIM ,  Do Sun HONG

    IPC分类号： G11C29/38 ,  G06F3/06 ,  G11C29/36

    摘要： A nonvolatile memory system may include a nonvolatile memory device, a delegate page attacker, and a health status analyzer. The nonvolatile memory device may include at least one memory block including a plurality of storage pages and a delegate page. The delegate page attacker may be configured to attack a bit of the delegate page at the same corresponding location as a bit of the storage page in which an error occurs. The health status analyzer may be configured to perform write and read operations for the delegate page and analyzes error information occurred in the write and read operations to determine whether the nonvolatile memory device is in a failure status.

    MEMORY APPARATUS AND METHOD OF WEAR-LEVELING OF A MEMORY APPARATUS
    4.
    发明申请
    MEMORY APPARATUS AND METHOD OF WEAR-LEVELING OF A MEMORY APPARATUS 审中-公开

    公开(公告)号：US20190171561A1

    公开(公告)日：2019-06-06

    申请号：US16271431

    申请日：2019-02-08

    申请人： SK hynix Inc.

    发明人： Donggun KIM ,  Yong Ju KIM ,  Do Sun HONG

    IPC分类号： G06F12/02

    摘要： A memory apparatus and a method of wear-leveling of a memory apparatus may be provided. The memory apparatus may include a memory having a plurality of storage blocks and a plurality of free blocks. The memory apparatus may include a memory controller configured for performing a first global wear-leveling to move data of a first storage block, which is a hot block among the storage blocks, to a first free block among the free blocks. The memory apparatus may include a memory controller configured for remapping a result of a logic operation of a logical page address of each of the pages in the first storage block and a first security refresh key to a physical page address of each of the pages in the first free block.

    RESISTANCE VARIABLE MEMORY APPARATUS, AND CIRCUIT AND METHOD FOR OPERATING THEREFOR
    5.
    发明申请
    RESISTANCE VARIABLE MEMORY APPARATUS, AND CIRCUIT AND METHOD FOR OPERATING THEREFOR 审中-公开

    公开(公告)号：US20190146674A1

    公开(公告)日：2019-05-16

    申请号：US16224623

    申请日：2018-12-18

    申请人： SK hynix Inc.

    发明人： Do-Sun HONG ,  Donggun KIM ,  Yong Ju KIM ,  Sang Gu JO

    IPC分类号： G06F3/06 ,  G06F11/07 ,  G06F12/02 ,  G11C13/00

    摘要： A resistance variable memory apparatus may include a memory circuit configured to include a plurality of blocks, each including a plurality of memory cells. The resistance variable memory apparatus may include a disturbance preventing circuit configured to be driven based on a counting signal corresponding to the number of write accesses for each of the plurality of blocks, a write command, and an address signal and to allow scrubbing to be performed on a memory cell having a preset scrubbing condition when the counting signal satisfied with the scrubbing condition is output based on the scribing condition according to a physical position of the memory cell in the block.

    SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SYSTEM
    7.
    发明申请
    SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SYSTEM 审中-公开

    公开(公告)号：US20180052732A1

    公开(公告)日：2018-02-22

    申请号：US15469047

    申请日：2017-03-24

    申请人： SK hynix Inc.

    发明人： Sang Gu JO ,  Jung Hyun KWON ,  Donggun KIM ,  Yong Ju KIM ,  Sungeun LEE ,  Jae Sun LEE ,  JINGZHE XU ,  Do-Sun HONG

    IPC分类号： G06F11/10 ,  G11C29/52

    CPC分类号： G06F11/1048 ,  G11C29/52 ,  G11C2029/0401

    摘要： A semiconductor system may be provided. The semiconductor system may include a first semiconductor device configured for outputting a transmission command and a transmission address, being inputted with and outputting transmission data, and generating an error flag signal when an error bit is included in the transmission data inputted in a read operation. The semiconductor system may include a second semiconductor device configured for storing the transmission address in a lookup table circuit when the error flag signal is enabled, and comparing the transmission address and a storage address stored in the lookup table circuit when the read operation is performed based on the transmission command and outputting the transmission data from the lookup table circuit.