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公开(公告)号：US09793901B2
公开(公告)日：2017-10-17
申请号：US14994291
申请日：2016-01-13
Applicant: SK hynix Inc.
Inventor： Han-Kyu Chi , Kyung-Hoon Kim , Myeong-Jae Park , Taek-Sang Song , Tae-Wook Kang
CPC classification number: H03L7/0807 , G11C7/222 , G11C11/4076 , H03K5/135 , H03K2005/00019 , H03L7/081 , H03L7/0812 , H03L7/105 , H03L2207/06 , H04L7/0037 , H04L7/0331
Abstract: An integrated circuit may include: a phase detector suitable for generating a delay control signal by comparing the phases of first and second clock signals to first and second target positions, a variable delay unit suitable for shifting the first and second clock signals to the first and second target positions, respectively, in response to the delay control signal, and a position controller suitable for varying the first and second target positions according to an operation mode.
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公开(公告)号：US09667261B2
公开(公告)日：2017-05-30
申请号：US14934410
申请日：2015-11-06
Applicant: SK hynix Inc.
Inventor： Han-Kyu Chi , Taek-Sang Song
CPC classification number: H03L7/0807 , H03L7/0814 , H03L7/089 , H03L7/093 , H04L7/0025 , H04L7/033 , H04L7/0337
Abstract: An integrated circuit includes a comparator capable of generating an up/down signal by comparing a feedback signal with a reference signal; a restoration signal generation unit capable of enabling a restoration signal when the up/down signal maintains an identical value for greater than or equal to a first specific time and changes afterwards; a processing circuit including one or more stages for sequentially processing the up/down signal, wherein a last one of the one or more stages holds a process result thereof for a second specific time when the restoration signal is enabled; and a feedback unit capable of generating the feedback signal in response to the process result of the last stage.
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公开(公告)号：US09270275B2
公开(公告)日：2016-02-23
申请号：US14300919
申请日：2014-06-10
Applicant: SK hynix Inc.
Inventor： Taek-Sang Song
IPC: H03L5/00 , H03K19/0185 , H03K17/16
CPC classification number: H03K19/0185 , H03K3/356191 , H03K17/161
Abstract: A level shifter includes a level shifting unit suitable for changing a swing voltage level of an input signal from a first swing voltage level to a second swing voltage level based on a clock signal, a precharging unit suitable for precharging an output node of the level shifting unit based on the clock signal, and an output unit suitable for latching a signal of the output node having the second swing voltage level to output as an output signal.
Abstract translation: 电平移位器包括电平移位单元，其适于基于时钟信号将输入信号的摆动电压电平从第一摆幅电压电平改变到第二摆幅电压电平;预充电单元，适于对电平移位的输出节点进行预充电 基于时钟信号的单元，以及适于锁存具有第二摆幅电压电平的输出节点的信号作为输出信号输出的输出单元。
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公开(公告)号：US10318187B2
公开(公告)日：2019-06-11
申请号：US15234912
申请日：2016-08-11
Applicant: SK hynix Inc.
Inventor： Il Park , Sang-Jin Byeon , Taek-Sang Song
IPC: G06F3/06 , G11C11/406 , G06F13/16
Abstract: A memory system includes: a memory device including a plurality of memory banks; and a memory controller suitable for monitoring a workload of the memory device and applying one of a first refresh command and a second refresh command to the memory device according to a result of the monitoring. In the memory device, the number of memory banks to be refreshed by the second refresh command may be greater than the number of memory banks to be refreshed by the first refresh command.
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5.发明授权Filtering circuit, phase identity determination circuit and delay locked loop 有权滤波电路，相位识别确定电路和延迟锁定环公开(公告)号：US09225346B2
公开(公告)日：2015-12-29
申请号：US14159193
申请日：2014-01-20
Applicant: SK hynix Inc.
Inventor： Dae-Han Kwon , Yong-Ju Kim , Taek-Sang Song
CPC classification number: H03L7/093 , H03L7/0812 , H03L7/235
Abstract: A filtering circuit includes a clock selection unit configured to transfer a first clock or a second clock having a frequency lower than the first clock as an operating clock in response to a frequence signal, and a filter configured to filter an input signal and generate a filtered signal in synchronization with the operating clock.
Abstract translation: 滤波电路包括时钟选择单元，其被配置为响应于频率信号将具有低于第一时钟的频率的第一时钟或第二时钟作为工作时钟传送;以及滤波器，被配置为滤波输入信号并生成滤波的 信号与操作时钟同步。
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Patent Agency Ranking
6.发明授权Data output circuit and operating method with reduced current overlap for semiconductor device 有权数据输出电路和半导体器件电流重叠减少的操作方法公开(公告)号：US09071241B2
公开(公告)日：2015-06-30
申请号：US13708562
申请日：2012-12-07
Applicant: SK hynix Inc.
Inventor： Kwan-Su Shon , Taek-Sang Song
IPC: H03K19/0175 , G06F1/10 , H03K19/003 , H03K19/096
CPC classification number: H03K19/017509 , G06F1/10 , H03K19/00315 , H03K19/00369 , H03K19/0963
Abstract: A semiconductor device includes a clock delay unit configured to delay a source clock by a given delay amount and generate a delayed source clock, a driving signal generation unit configured to decide logic levels of first and second driving signals based on a value of input data, to select one of the source clock and the delayed source clock based on current logic levels of the first and second driving signal's, which are detected based on the source clock, and to use a selected clock as a reference of an operation for determining next logic levels of the first and second driving signals, and an output pad driving unit configured to drive a data output pad with a first voltage in response to the first driving signal, and to drive the data output pad with a second voltage in response to the second driving signal.
Abstract translation: 一种半导体器件，包括：时钟延迟单元，被配置为将源时钟延迟给定延迟量并产生延迟的源时钟;驱动信号生成单元，被配置为基于输入数据的值来确定第一和第二驱动信号的逻辑电平; 基于基于源时钟检测到的第一和第二驱动信号的当前逻辑电平来选择源时钟和延迟源时钟中的一个，并且使用所选择的时钟作为用于确定下一个逻辑的操作的参考 第一驱动信号和第二驱动信号的电平，以及输出焊盘驱动单元，被配置为响应于第一驱动信号而以第一电压驱动数据输出焊盘，并且响应于第二驱动信号而以第二电压驱动数据输出焊盘 驾驶信号。
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7.发明授权Phase interpolator circuit, clock data recovery circuit including the same, and phase interpolation method 有权相位内插器电路，包括相位的时钟数据恢复电路和相位插值方法公开(公告)号：US09379881B1
公开(公告)日：2016-06-28
申请号：US14749342
申请日：2015-06-24
Applicant: SK hynix Inc.
Inventor： Han-Kyu Chi , Taek-Sang Song
CPC classification number: H04L7/0025 , H03K5/135 , H03K2005/00052 , H04L7/0008 , H04L7/0337
Abstract: A phase interpolator circuit that includes an interpolator suitable for generating synthesized clocks through synthesizing two multi-phase clocks; and an interpolation code generator suitable for generating an interpolation code for controlling the interpolator in response to a shift request. The interpolation code generator generates the interpolation code so that a (K+1)-th multi-phase clock is output as the synthesized clock when a phase of the synthesized clock is to be changed from a phase between K-th and (K+1)-th multi-phase clocks to a phase between (K+1)-th and (K+2)-th multi-phase clocks in response to a multi-shift-up request.
Abstract translation: 一种相位插值器电路，包括适于通过合成两个多相时钟产生合成时钟的内插器; 以及内插代码发生器，其适于产生用于响应于移位请求来控制所述内插器的内插代码。 内插码发生器产生内插码，使得当从第K和（K + 1）之间的相位改变合成时钟的相位时，输出第（K + 1）个多相时钟作为合成时钟， 1）多相时钟响应于多次上移请求到（K + 1）和（K + 2）个多相时钟之间的相位。
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公开(公告)号：US09059825B2
公开(公告)日：2015-06-16
申请号：US14498296
申请日：2014-09-26
Applicant: SK HYNIX INC. , Seoul National University R&DB Foundation
Inventor： Han-Kyu Chi , Taek-Sang Song , Seok-Min Ye , Gi-Moon Hong , Woo-Rham Bae , Min-Seong Chu , Deog-Kyoon Jeong , Su-Hwan Kim
CPC classification number: H04L7/0041 , H03K5/131 , H03K5/135 , H03K2005/0011 , H04L7/0008 , H04L7/0338 , H04L7/10 , H04L25/03057 , H04L25/14
Abstract: A receiver includes a fixed delay unit configured to delay a first clock signal received from a clock channel by a predetermined time and output a second clock signal; a first delay unit configured to delay the first clock signal in response to a first control signal; a first data sampler configured to sample a data signal received from a data channel in response to an output signal of the first delay unit and output a first data signal; a second delay unit configured to delay the first data signal in response to a second control signal and output a second data signal; a second data sampler configured to sample the second data signal in response to the second clock signal; and a delay controller configured to output the first control signal and the second control signal.
Abstract translation: 接收机包括固定延迟单元，其被配置为将从时钟信道接收的第一时钟信号延迟预定时间并输出第二时钟信号; 第一延迟单元，被配置为响应于第一控制信号延迟所述第一时钟信号; 第一数据采样器，被配置为响应于所述第一延迟单元的输出信号对从数据信道接收的数据信号进行采样，并输出第一数据信号; 第二延迟单元，被配置为响应于第二控制信号延迟所述第一数据信号并输出第二数据信号; 第二数据采样器，被配置为响应于所述第二时钟信号对所述第二数据信号进行采样; 以及延迟控制器，被配置为输出第一控制信号和第二控制信号。
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公开(公告)号：US09013222B2
公开(公告)日：2015-04-21
申请号：US13970192
申请日：2013-08-19
Applicant: SK Hynix Inc.
Inventor： Taek-Sang Song
CPC classification number: H04L25/00 , H04L25/03878
Abstract: An equalizer circuit includes an input terminal, a pull-up driving unit suitable for pull-up driving an output terminal based on a signal of the input terminal, a pull-down driving unit suitable for pull-down driving the output terminal, and a capacitor connected between the input terminal and the output terminal.
Abstract translation: 均衡器电路包括输入端子，适于基于输入端子的信号上拉驱动输出端子的上拉驱动单元，适于下拉驱动输出端子的下拉驱动单元，以及 电容器连接在输入端子和输出端子之间。
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公开(公告)号：US09843325B2
公开(公告)日：2017-12-12
申请号：US15378847
申请日：2016-12-14
Applicant: SK hynix Inc.
Inventor： Taek-Sang Song
IPC: H03M9/00 , H03K19/0185
CPC classification number: H03K19/018528 , H03M9/00
Abstract: A level shifter circuit includes a level shifting unit configured to receive signals that may vary in a first range via a positive input terminal and a negative input terminal, respectively and to output signals that may vary in a second range to a positive output terminal and a negative output terminal, respectively, where the second range is larger than the first range, a first pre-charging unit configured to pre-charge the positive output terminal to a predetermined level when a clock is in a first level, and a second pre-charging unit configured to pre-charge the negative output terminal to the predetermined level when the clock is in the first level.
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