公开(公告)号：US09536861B2

公开(公告)日：2017-01-03

申请号：US14692429

申请日：2015-04-21

Applicant: SK hynix Inc.

Inventor： Jae Woong Yu ,  Jong Seo Jung ,  So Hyun Jung ,  Seong Cheol Shin

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/13 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L25/18

CPC classification number: H01L25/0652 ,  H01L23/13 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3142 ,  H01L23/49816 ,  H01L23/5384 ,  H01L24/06 ,  H01L24/32 ,  H01L24/33 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/92 ,  H01L25/18 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4824 ,  H01L2224/49175 ,  H01L2224/73215 ,  H01L2224/92147 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/1815 ,  H01L2924/18165 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A semiconductor package may include a substrate having a first surface and a second surface facing away from the first surface, a window defined through a center portion of the substrate, and a plurality of first bond fingers, a plurality of second bond fingers, and a plurality of external electrodes arranged on the second surface; two or more first semiconductor chips each having a plurality of first bonding pads arranged adjacent to edges of the first semiconductor chips, and each of the first semiconductor chips separately attached to the first surface of the substrate in a face-down type position exposing the first bonding pads; and a second semiconductor chip having a plurality of second bonding pads arranged at a center portion of the second semiconductor chip, and attached to each of the first semiconductor chips in a face-down type position exposing the second bonding pads through the window.

Abstract translation: 半导体封装可以包括具有第一表面和背离第一表面的第二表面的衬底，通过衬底的中心部分限定的窗口，以及多个第一结合指状物，多个第二结合指状物和 布置在第二表面上的多个外部电极; 两个或更多个第一半导体芯片，每个半导体芯片具有与第一半导体芯片的边缘相邻布置的多个第一焊盘，并且每个第一半导体芯片以面朝下的型式分别附接到基板的第一表面， 焊盘; 以及第二半导体芯片，其具有布置在所述第二半导体芯片的中心部分的多个第二接合焊盘，并且以面朝下型位置附接到每个所述第一半导体芯片，所述第二半导体芯片通过所述窗口暴露所述第二接合焊盘。

公开(公告)号：US09209146B2

公开(公告)日：2015-12-08

申请号：US14532393

申请日：2014-11-04

Applicant: SK hynix Inc.

Inventor： Seung Jee Kim ,  Qwan Ho Chung ,  Jong Hyun Nam ,  Si Han Kim ,  Sang Yong Lee ,  Seong Cheol Shin

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L21/768 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L24/11 ,  H01L21/56 ,  H01L21/768 ,  H01L23/3121 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/19 ,  H01L24/83 ,  H01L2224/02333 ,  H01L2224/02351 ,  H01L2224/02372 ,  H01L2224/02379 ,  H01L2224/03334 ,  H01L2224/0346 ,  H01L2224/03472 ,  H01L2224/03474 ,  H01L2224/03903 ,  H01L2224/03906 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05017 ,  H01L2224/05026 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/11334 ,  H01L2224/11602 ,  H01L2224/1184 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/211 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2924/00

Abstract: An electronic device package includes a bump having a post disposed on a contact portion of a semiconductor chip and an enlarged portion laterally protruded from an upper portion of the post; an interconnection portion having a locking portion that substantially surrounds the enlarged portion and an upper sidewall of the post; and a dielectric layer substantially surrounding the bump and the locking portion to separate the interconnection portion from the semiconductor chip.

Abstract translation: 电子器件封装包括具有设置在半导体芯片的接触部分上的柱和从柱的上部侧向突出的扩大部分的凸块; 互连部分，其具有基本上围绕所述柱的扩大部分和上侧壁的锁定部分; 以及基本上围绕所述凸起和所述锁定部分的绝缘层，以将所述互连部分与所述半导体芯片分离。