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    Electronic device and method for fabricating the same
    3.
    发明授权
    Electronic device and method for fabricating the same 有权

    公开(公告)号：US09734060B2

    公开(公告)日：2017-08-15

    申请号：US14789428

    申请日：2015-07-01

    申请人： SK hynix Inc.

    发明人： Cha-Deok Dong ,  Ki-Seon Park ,  Bo-Mi Lee ,  Won-Joon Choi ,  Guk-Cheon Kim ,  Yang-Kon Kim

    IPC分类号： G06F12/08 ,  G06F12/0802 ,  H01L43/08 ,  H01L43/10 ,  H01L27/22

    CPC分类号： G06F12/0802 ,  G06F2212/1028 ,  G06F2212/202 ,  G06F2212/222 ,  H01L27/222 ,  H01L43/08 ,  H01L43/10

    摘要： An electronic device is provided to include a semiconductor memory that includes: a substrate including a first region and a second region different from the first region; an interlayer dielectric layer formed over the substrate; a first conductive pattern located over the first region and formed in the interlayer dielectric layer, the first conductive pattern including a planarized top surface with a top surface of the interlayer dielectric layer; a second conductive pattern located over the second region and formed in the interlayer dielectric layer, the second conductive pattern including at least a portion recessed below a top surface of the interlayer dielectric layer; a variable resistance pattern formed over the interlayer dielectric layer the variable resistance pattern having a bottom surface coupled to the first conductive pattern and exhibiting different resistance values; and a capping layer pattern formed over the variable resistance pattern.

    Electronic device and method for fabricating the same
    4.
    发明授权
    Electronic device and method for fabricating the same 有权

    公开(公告)号：US09722172B2

    公开(公告)日：2017-08-01

    申请号：US14789798

    申请日：2015-07-01

    申请人： SK hynix Inc.

    发明人： Ki-Seon Park ,  Bo-Mi Lee ,  Won-Joon Choi ,  Guk-Cheon Kim

    IPC分类号： G06F12/00 ,  H01L43/08 ,  H01L43/02 ,  H01L43/12 ,  G06F1/32

    CPC分类号： H01L43/08 ,  G06F1/3275 ,  H01L43/02 ,  H01L43/12

    摘要： This technology provides an electronic device and a method for fabricating the same. An electronic device in accordance with an implementation of this document includes semiconductor memory, and the semiconductor memory includes an interlayer dielectric layer formed over a substrate and having a hole; a conductive pattern filled in the hole and having a top surface located at a level substantially same as a top surface of the interlayer dielectric layer; and an MTJ (Magnetic Tunnel Junction) structure formed over the conductive pattern to be coupled to the conductive pattern and including a free layer having a variable magnetization direction, a pinned layer having a pinned magnetization direction and a tunnel barrier layer interposed between the free layer and the pinned layer, wherein an upper portion of the conductive pattern includes a first amorphous region.

    ELECTRONIC DEVICE
    6.
    发明申请
    ELECTRONIC DEVICE 审中-公开

    公开(公告)号：US20170200487A1

    公开(公告)日：2017-07-13

    申请号：US15469238

    申请日：2017-03-24

    申请人： SK hynix Inc.

    发明人： Guk-Cheon Kim ,  Ki-Seon Park ,  Bo-Mi Lee ,  Won-Joon Choi ,  Yang-Kon Kim

    IPC分类号： G11C11/16 ,  H01L27/22 ,  H01L43/08 ,  H01L43/02 ,  H01L43/10

    CPC分类号： H01L43/08 ,  G11C11/161 ,  H01L27/222 ,  H01L43/10

    摘要： Disclosed are an electronic device comprising a semiconductor memory. The semiconductor memory includes a variable resistance element including a free layer having a variable magnetization direction; a pinned layer having a fixed magnetization direction; and a tunnel barrier layer interposed between the free layer and the pinned layer, wherein the free layer includes: a first free layer adjacent to the tunnel barrier layer and having a perpendicular magnetic anisotropy at an interface with the tunnel barrier layer; and a second free layer spaced apart from the tunnel barrier layer by the first free layer and having a saturation magnetization lower than a saturation magnetization of the first free layer.

    Vertical channel type nonvolatile memory device and method for fabricating the same
    8.
    发明授权
    Vertical channel type nonvolatile memory device and method for fabricating the same 有权
    垂直通道型非易失性存储器件及其制造方法

    公开(公告)号：US09165924B2

    公开(公告)日：2015-10-20

    申请号：US13788319

    申请日：2013-03-07

    申请人： SK hynix Inc.

    发明人： Heung-Jae Cho ,  Yong-Soo Kim ,  Beom-Yong Kim ,  Won-Joon Choi ,  Jung-Ryul Ahn

    IPC分类号： H01L29/792 ,  H01L27/088 ,  H01L27/115

    CPC分类号： H01L27/088 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/792 ,  H01L29/7926

    摘要： A method for fabricating a vertical channel type nonvolatile memory device includes: alternately forming a plurality of sacrificial layers and a plurality of interlayer dielectric layers over a semiconductor substrate; etching the sacrificial layers and the interlayer dielectric layers to form a plurality of first openings for channel each of which exposes the substrate; filling the first openings to form a plurality of channels protruding from the semiconductor substrate; etching the sacrificial layers and the interlayer dielectric layers to form second openings for removal of the sacrificial layers between the channels; exposing side walls of the channels by removing the sacrificial layers exposed by the second openings; and forming a tunnel insulation layer, a charge trap layer, a charge blocking layer, and a conductive layer for gate electrode on the exposed sidewalls of the channels.

    摘要翻译： 一种用于制造垂直沟道型非易失性存储器件的方法包括：在半导体衬底上交替地形成多个牺牲层和多个层间电介质层; 蚀刻牺牲层和层间电介质层以形成多个用于通道的第一开口，每个开口暴露衬底; 填充第一开口以形成从半导体衬底突出的多个通道; 蚀刻牺牲层和层间电介质层以形成用于去除沟道之间的牺牲层的第二开口; 通过去除由第二开口暴露的牺牲层来暴露通道的侧壁; 以及在通道的暴露的侧壁上形成隧道绝缘层，电荷陷阱层，电荷阻挡层和用于栅电极的导电层。