公开(公告)号：US09865651B2

公开(公告)日：2018-01-09

申请号：US15182499

申请日：2016-06-14

Applicant: SK hynix Inc.

Inventor： Jong-Chul Lee ,  Beom-Yong Kim ,  Hyung-Dong Lee

IPC: H01L27/24 ,  H01L45/00 ,  H01L27/22 ,  H01L27/11507 ,  H01L27/1159 ,  G06F3/06

CPC classification number: H01L27/2427 ,  G06F3/061 ,  G06F3/0659 ,  G06F3/0679 ,  H01L27/11507 ,  H01L27/1159 ,  H01L27/224 ,  H01L45/08 ,  H01L45/10 ,  H01L45/1233 ,  H01L45/1253

Abstract: A threshold switching device may include: a first electrode layer; a second electrode layer; a first insulating layer interposed between the first and second electrode layers, and provided adjacent to the first electrode layer; and a second insulating layer interposed between the first and second electrode layers, and provided adjacent to the second electrode layer, wherein the first and second insulating layers contain a plurality of neutral defects, a concentration of the plurality of neutral defects being at a maximum along a first interface between the first insulating layer and the second insulating layer, and wherein the threshold switching device has an ON or OFF state according to whether electrons are ejected from the plurality of neutral defects.

公开(公告)号：US09704921B2

公开(公告)日：2017-07-11

申请号：US14662198

申请日：2015-03-18

Applicant: SK hynix Inc.

Inventor： Jong-Gi Kim ,  Ki-Jeung Lee ,  Beom-Yong Kim

IPC: G06F12/00 ,  H01L27/24 ,  H01L45/00 ,  G06F12/0802 ,  G06F13/16

CPC classification number: H01L27/2427 ,  G06F12/0802 ,  G06F13/1663 ,  G06F13/1673 ,  G06F2212/40 ,  H01L27/2409 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16

Abstract: Provided is an electronic device including a switching element, wherein the switching element may include a first electrode, a second electrode, a switching layer interposed between the first and second electrodes, and a first amorphous semiconductor layer interposed between the first electrode and the switching layer.

公开(公告)号：US09165924B2

公开(公告)日：2015-10-20

申请号：US13788319

申请日：2013-03-07

Applicant: SK hynix Inc.

Inventor： Heung-Jae Cho ,  Yong-Soo Kim ,  Beom-Yong Kim ,  Won-Joon Choi ,  Jung-Ryul Ahn

IPC: H01L29/792 ,  H01L27/088 ,  H01L27/115

CPC classification number: H01L27/088 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/792 ,  H01L29/7926

Abstract: A method for fabricating a vertical channel type nonvolatile memory device includes: alternately forming a plurality of sacrificial layers and a plurality of interlayer dielectric layers over a semiconductor substrate; etching the sacrificial layers and the interlayer dielectric layers to form a plurality of first openings for channel each of which exposes the substrate; filling the first openings to form a plurality of channels protruding from the semiconductor substrate; etching the sacrificial layers and the interlayer dielectric layers to form second openings for removal of the sacrificial layers between the channels; exposing side walls of the channels by removing the sacrificial layers exposed by the second openings; and forming a tunnel insulation layer, a charge trap layer, a charge blocking layer, and a conductive layer for gate electrode on the exposed sidewalls of the channels.

Abstract translation: 一种用于制造垂直沟道型非易失性存储器件的方法包括：在半导体衬底上交替地形成多个牺牲层和多个层间电介质层; 蚀刻牺牲层和层间电介质层以形成多个用于通道的第一开口，每个开口暴露衬底; 填充第一开口以形成从半导体衬底突出的多个通道; 蚀刻牺牲层和层间电介质层以形成用于去除沟道之间的牺牲层的第二开口; 通过去除由第二开口暴露的牺牲层来暴露通道的侧壁; 以及在通道的暴露的侧壁上形成隧道绝缘层，电荷陷阱层，电荷阻挡层和用于栅电极的导电层。

公开(公告)号：US11855172B2

公开(公告)日：2023-12-26

申请号：US17741204

申请日：2022-05-10

Applicant: SK hynix Inc.

Inventor： Beom-Yong Kim

IPC: H01L29/51 ,  H01L29/49 ,  H01L29/06 ,  H01L29/94 ,  H01L21/28 ,  H01L49/02 ,  H10B12/00

CPC classification number: H01L29/517 ,  H01L21/28088 ,  H01L28/60 ,  H01L29/0607 ,  H01L29/4966 ,  H01L29/94 ,  H10B12/30

Abstract: A semiconductor layer stack includes a first conductive layer, a dielectric layer including a high-k material, which is formed on the first conductive layer, a second conductive layer formed on the dielectric layer, and an interface control layer formed between the dielectric layer and the second conductive layer and including a leakage blocking material, a dopant material, a high bandgap material and a high work function material.

公开(公告)号：US10347711B2

公开(公告)日：2019-07-09

申请号：US16002866

申请日：2018-06-07

Applicant: SK hynix Inc.

Inventor： Beom-Yong Kim ,  Deok-Sin Kil ,  Hee-Young Jeon

IPC: H01L21/8242 ,  H01L49/02 ,  H01G4/12 ,  H01G4/005

Abstract: A method for fabricating a capacitor includes: forming a bottom electrode; forming a dielectric layer on the bottom electrode; forming a metal oxide layer including a metal having a high electronegativity on the dielectric layer; forming a sacrificial layer on the metal oxide layer to reduce the metal oxide layer to a metal layer; and forming a top electrode on the sacrificial layer to convert the reduced metal layer into a high work function interface layer.

公开(公告)号：US09659828B2

公开(公告)日：2017-05-23

申请号：US15085682

申请日：2016-03-30

Applicant: SK hynix Inc.

Inventor： Yun-Hyuck Ji ,  Beom-Yong Kim ,  Seung-Mi Lee

IPC: H01L21/82 ,  H01L21/8238 ,  H01L21/28 ,  H01L29/49 ,  H01L21/02 ,  H01L29/51

CPC classification number: H01L21/823842 ,  H01L21/02148 ,  H01L21/02274 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/28202 ,  H01L21/28247 ,  H01L21/823807 ,  H01L21/823828 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/518

Abstract: A semiconductor device includes a gate dielectric layer over a substrate, a metal layer over the gate dielectric layer, a capping layer over the metal layer, wherein the capping layer includes a plurality of dipole forming elements concentrated at the interface between the metal layer and the capping layer.

公开(公告)号：US10593777B2

公开(公告)日：2020-03-17

申请号：US16233582

申请日：2018-12-27

Applicant: SK hynix Inc.

Inventor： Beom-Yong Kim

IPC: H01L29/76 ,  H01L29/51 ,  H01L29/49 ,  H01L29/06 ,  H01L29/94 ,  H01L21/28 ,  H01L49/02 ,  H01L27/108

Abstract: A semiconductor layer stack includes a first conductive layer, a dielectric layer including a high-k material, which is formed on the first conductive layer, a second conductive layer formed on the dielectric layer, and an interface control layer formed between the dielectric layer and the second conductive layer and including a leakage blocking material, a dopant material, a high bandgap material and a high work function material.

公开(公告)号：US09385311B2

公开(公告)日：2016-07-05

申请号：US14817031

申请日：2015-08-03

Applicant: SK hynix Inc.

Inventor： Beom-Yong Kim ,  Kee-Jeung Lee ,  Wan-Gee Kim ,  Hyo-June Kim

IPC: H01L45/00 ,  G11C13/00 ,  H01L27/24

CPC classification number: H01L45/085 ,  G11C13/0004 ,  G11C13/0007 ,  G11C2213/55 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1293 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147

Abstract: A semiconductor device includes a first conductive layer, a second conductive layer spaced from the first conductive layer, a variable resistance layer interposed between the first and second conductive layers, and an impurity-doped layer provided over a side surface of the variable resistance layer. The variable resistance layer has a smaller width than the first and the second conductive layers.

公开(公告)号：US09064567B2

公开(公告)日：2015-06-23

申请号：US14249251

申请日：2014-04-09

Applicant: SK HYNIX INC.

Inventor： Beom-Yong Kim

IPC: G11C13/00 ,  H01L45/00

CPC classification number: G11C13/0007 ,  G11C13/0021 ,  G11C2213/31 ,  G11C2213/33 ,  G11C2213/77 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147

Abstract: An electronic device includes a semiconductor memory unit. The semiconductor memory unit includes first lines extending along a first direction; second lines extending along a second direction that intersects with the first direction; a silicon-added metal oxide layer disposed in each intersection region of the first lines and the second lines; a metal oxide layer that is disposed alternately with the silicon-added metal oxide layer in the first direction and that is disposed in a region between two adjacent second lines and over a corresponding one of the first lines over which the silicon-added metal oxide layer is disposed; and a silicon oxide layer that is disposed alternately with the silicon-added metal oxide layer in the second direction and that is disposed in a region between two first lines and under a corresponding one of the second lines under which the silicon-added metal oxide layer is disposed.

Abstract translation: 电子设备包括半导体存储单元。 半导体存储单元包括沿着第一方向延伸的第一线; 沿着与第一方向相交的第二方向延伸的第二线; 设置在第一线和第二线的每个交叉区域中的添加有硅的金属氧化物层; 金属氧化物层，其在第一方向上与添加了硅的金属氧化物层交替设置并且设置在两个相邻的第二线之间的区域中，并且在相应的第一线之上，添加有硅的金属氧化物层 被处置 以及氧化硅层，其与所述添加硅的金属氧化物层沿第二方向交替布置，并且设置在两个第一线之间的区域中，并且在相应的一条第二线下方，所述添加了硅的金属氧化物层 被处置。

公开(公告)号：US09035274B2

公开(公告)日：2015-05-19

申请号：US13945834

申请日：2013-07-18

Applicant: SK HYNIX INC.

Inventor： Beom-Yong Kim

IPC: H01L47/00 ,  H01L45/00 ,  H01L27/24 ,  G11C13/00

CPC classification number: H01L45/08 ,  G11C13/0002 ,  G11C2213/30 ,  H01L27/2481 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/146 ,  H01L45/1658

Abstract: A method for fabricating a semiconductor device includes forming an impurity layer over a first conductive layer; forming a first metal oxide layer over the impurity layer, wherein the first metal oxide layer includes oxygen at a lower ratio than a stoichiometric ratio; diffusing an impurity from the impurity layer into the first metal oxide layer to form a first doped metal oxide layer; forming a second metal oxide layer over the first doped metal oxide layer; and forming a second conductive layer over the second metal oxide layer.

Abstract translation: 一种制造半导体器件的方法包括在第一导电层上形成杂质层; 在所述杂质层上形成第一金属氧化物层，其中所述第一金属氧化物层包括比化学计量比低的氧; 将杂质从杂质层扩散到第一金属氧化物层中以形成第一掺杂金属氧化物层; 在所述第一掺杂金属氧化物层上形成第二金属氧化物层; 以及在所述第二金属氧化物层上形成第二导电层。