公开(公告)号：US20150028496A1

公开(公告)日：2015-01-29

申请号：US14514190

申请日：2014-10-14

Applicant: STATS CHIPPAC, LTD.

Inventor： Henry D. Bathan ,  Zigmund R. Camacho ,  Jairus L. Pisigan

IPC: H01L25/065 ,  H01L21/56 ,  H01L21/768

CPC classification number: H01L25/0657 ,  H01L21/56 ,  H01L21/568 ,  H01L21/768 ,  H01L24/11 ,  H01L24/16 ,  H01L24/17 ,  H01L24/48 ,  H01L24/81 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81001 ,  H01L2224/81194 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2225/06586 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15174 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A semiconductor device is made by forming first and second interconnect structures over a first semiconductor die. A third interconnect structure is formed in proximity to the first die. A second semiconductor die is mounted over the second and third interconnect structures. An encapsulant is deposited over the first and second die and first, second, and third interconnect structures. A backside of the second die is substantially coplanar with the first interconnect structure and a backside of the first semiconductor die is substantially coplanar with the third interconnect structure. The first interconnect structure has a height which is substantially the same as a combination of a height of the second interconnect structure and a thickness of the second die. The third interconnect structure has a height which is substantially the same as a combination of a height of the second interconnect structure and a thickness of the first die.

Abstract translation: 通过在第一半导体管芯上形成第一和第二互连结构来制造半导体器件。 在第一管芯附近形成第三互连结构。 第二半导体管芯安装在第二和第三互连结构上。 密封剂沉积在第一和第二管芯以及第一，第二和第三互连结构上。 第二管芯的背面基本上与第一互连结构共面，并且第一半导体管芯的背面基本上与第三互连结构共面。 第一互连结构具有与第二互连结构的高度和第二管芯的厚度的组合基本相同的高度。 第三互连结构具有与第二互连结构的高度和第一管芯的厚度的组合基本相同的高度。

公开(公告)号：US09721925B2

公开(公告)日：2017-08-01

申请号：US14514190

申请日：2014-10-14

Applicant: STATS ChipPAC, Ltd.

Inventor： Henry D. Bathan ,  Zigmund R. Camacho ,  Jairus L. Pisigan

IPC: H01L25/065 ,  H01L21/56 ,  H01L21/768 ,  H01L25/10 ,  H01L25/18 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L21/56 ,  H01L21/568 ,  H01L21/768 ,  H01L24/11 ,  H01L24/16 ,  H01L24/17 ,  H01L24/48 ,  H01L24/81 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81001 ,  H01L2224/81194 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2225/06586 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15174 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A semiconductor device is made by forming first and second interconnect structures over a first semiconductor die. A third interconnect structure is formed in proximity to the first die. A second semiconductor die is mounted over the second and third interconnect structures. An encapsulant is deposited over the first and second die and first, second, and third interconnect structures. A backside of the second die is substantially coplanar with the first interconnect structure and a backside of the first semiconductor die is substantially coplanar with the third interconnect structure. The first interconnect structure has a height which is substantially the same as a combination of a height of the second interconnect structure and a thickness of the second die. The third interconnect structure has a height which is substantially the same as a combination of a height of the second interconnect structure and a thickness of the first die.