公开(公告)号：US20180261551A1

公开(公告)日：2018-09-13

申请号：US15456972

申请日：2017-03-13

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Goo Lee ,  KyungMoon Kim ,  SooSan Park ,  KeoChang Lee

IPC: H01L23/552 ,  H01L21/56 ,  H01L21/3105 ,  H01L23/31 ,  H01L25/16 ,  H01L25/065 ,  H01L25/00 ,  H01L23/053 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L23/552 ,  H01L21/56 ,  H01L23/16 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5384 ,  H01L24/17 ,  H01L24/32 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/2919 ,  H01L2224/48091 ,  H01L2224/48179 ,  H01L2224/73265 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/1203 ,  H01L2924/1304 ,  H01L2924/1421 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/3025 ,  H01L2924/014 ,  H01L2224/45099

Abstract: A semiconductor device has a partition fence disposed between a first attach area and a second attach area on a substrate. A first electrical component is disposed over the first attach area. A second electrical component is disposed over the second attach area. The partition fence extends above and along a length of the first electrical component and second electrical component. An encapsulant is deposited over the substrate, first electrical component, second electrical component, and partition fence. A portion of the encapsulant is removed to expose a surface of the partition fence and planarizing the encapsulant. A shielding layer is formed over the encapsulant and in contact with the surface of the partition fence. The combination of the partition fence and shielding layer compartmentalize the first electrical component and second electrical component for physical and electrical isolation to reduce the influence of EMI, RFI, and other inter-device interference.

公开(公告)号：US10418332B2

公开(公告)日：2019-09-17

申请号：US15456972

申请日：2017-03-13

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Goo Lee ,  KyungMoon Kim ,  SooSan Park ,  KeoChang Lee

IPC: H01L23/552 ,  H01L21/56 ,  H01L25/00 ,  H01L23/00 ,  H01L25/16 ,  H01L25/065 ,  H01L23/538 ,  H01L23/16 ,  H01L23/31

Abstract: A semiconductor device has a partition fence disposed between a first attach area and a second attach area on a substrate. A first electrical component is disposed over the first attach area. A second electrical component is disposed over the second attach area. The partition fence extends above and along a length of the first electrical component and second electrical component. An encapsulant is deposited over the substrate, first electrical component, second electrical component, and partition fence. A portion of the encapsulant is removed to expose a surface of the partition fence and planarizing the encapsulant. A shielding layer is formed over the encapsulant and in contact with the surface of the partition fence. The combination of the partition fence and shielding layer compartmentalize the first electrical component and second electrical component for physical and electrical isolation to reduce the influence of EMI, RFI, and other inter-device interference.

公开(公告)号：US09859200B2

公开(公告)日：2018-01-02

申请号：US14792447

申请日：2015-07-06

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： SooSan Park ,  KyuSang Kim ,  YeoChan Ko ,  KeoChang Lee ,  HeeJo Chi ,  HeeSoo Lee

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/31 ,  H01L23/482 ,  H01L21/56 ,  H01L21/48 ,  H01L23/538

CPC classification number: H01L23/49833 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/56 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/3142 ,  H01L23/4828 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49894 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29387 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/83104 ,  H01L2224/92 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15331 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/05442 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A system and method of manufacture of an integrated circuit packaging system includes: a base substrate, the base substrate includes a base terminal; an integrated circuit device on the base substrate; a bottom conductive joint on the base terminal; a conductive ball on the bottom conductive joint, the conductive ball includes a core body; and an interposer over the conductive ball.