公开(公告)号：US20190221678A1

公开(公告)日：2019-07-18

申请号：US16246945

申请日：2019-01-14

Applicant: STMicroelectronics S.r.l.

Inventor： Flavio Francesco VILLA ,  Marco MORELLI ,  Marco MARCHESI ,  Simone Dario MARIANI ,  Fabrizio Fausto Renzo TOIA

IPC: H01L29/94 ,  H01L49/02 ,  H01L29/66

CPC classification number: H01L29/945 ,  H01L21/02639 ,  H01L21/0265 ,  H01L27/0629 ,  H01L28/60 ,  H01L29/66181

Abstract: A semiconductor body includes a front side and a back side and is configured to support an electronic circuit. A buried region is provided in the semiconductor body at a location between the electronic circuit and the back side. The buried region includes a layer of conductive material and a dielectric layer, where the dielectric layer is arranged between the layer of conductive material and the semiconductor body. A conductive path extends between the buried region and the front side to form a path for electrical access to the layer of conductive material. A capacitor is thus formed with the layer of conductive material providing a capacitor plate and the dielectric layer providing the capacitor dielectric. A further capacitor plate is provided by the semiconductor body, or by a further layer of conductive material in the buried region.

公开(公告)号：US20210143286A1

公开(公告)日：2021-05-13

申请号：US17153599

申请日：2021-01-20

Applicant: STMicroelectronics S.r.l.

Inventor： Flavio Francesco VILLA ,  Marco MORELLI ,  Marco MARCHESI ,  Simone Dario MARIANI ,  Fabrizio Fausto Renzo TOIA

IPC: H01L29/94 ,  H01L29/66 ,  H01L27/06 ,  H01L49/02

Abstract: A semiconductor body includes a front side and a back side and is configured to support an electronic circuit. A buried region is provided in the semiconductor body at a location between the electronic circuit and the back side. The buried region includes a layer of conductive material and a dielectric layer, where the dielectric layer is arranged between the layer of conductive material and the semiconductor body. A conductive path extends between the buried region and the front side to form a path for electrical access to the layer of conductive material. A capacitor is thus formed with the layer of conductive material providing a capacitor plate and the dielectric layer providing the capacitor dielectric. A further capacitor plate is provided by the semiconductor body, or by a further layer of conductive material in the buried region.

公开(公告)号：US20170030983A1

公开(公告)日：2017-02-02

申请号：US15142270

申请日：2016-04-29

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Marco CRESCENTINI ,  Marco TARTAGNI ,  Aldo ROMANI ,  Roberto CANEGALLO ,  Marco MARCHESI ,  Domenico CRISTAUDO

IPC: G01R33/07

CPC classification number: G01R33/075 ,  G01R15/20 ,  G01R33/0029 ,  G01R33/0206 ,  G01R33/028 ,  G01R33/0283 ,  G01R33/038 ,  G01R33/07 ,  G01R33/1215

Abstract: A Hall sensor may include a Hall sensing element configured to produce a Hall voltage indicative of a magnetic field when traversed by an electric current, and a first pair of bias electrodes mutually opposed in a first direction across the Hall sensing element. The Hall sensor may include a second pair of bias electrodes mutually opposed in a second direction across the Hall sensing element. The Hall sensor may include a first pair of sensing electrodes mutually opposed in a third direction across the Hall sensing element, and a second pair of sensing electrodes mutually opposed in a fourth direction across the Hall sensing element. The fourth direction may be orthogonal to the third direction, each sensing electrode being between a bias electrode of the first pair and a bias electrode of the second pair.

Abstract translation: 霍尔传感器可以包括霍尔传感元件，霍尔传感元件被配置为产生指示通过电流穿过的磁场的霍尔电压;以及第一对偏置电极，沿第一方向跨过霍尔感测元件相对。 霍尔传感器可以包括在霍尔感测元件上沿第二方向相互相对的第二对偏置电极。 霍尔传感器可以包括在霍尔感测元件上沿第三方向相互相对的第一对感测电极和在霍尔感测元件上沿第四方向相互相对的第二对感测电极。 第四方向可以与第三方向正交，每个感测电极位于第一对的偏置电极和第二对的偏置电极之间。

公开(公告)号：US20190165170A1

公开(公告)日：2019-05-30

申请号：US16264384

申请日：2019-01-31

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Marco SAMBI ,  Fabrizio Fausto Renzo TOIA ,  Marco MARCHESI ,  Marco MORELLI ,  Riccardo DEPETRO ,  Giuseppe BARILLARO ,  Lucanos Marsilio STRAMBINI

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/66 ,  H01L29/06 ,  H01L29/36 ,  H01L29/08 ,  H01L29/16 ,  H01L21/308 ,  H01L29/32 ,  H03K17/687 ,  H01L29/417 ,  H01L21/265 ,  H01L29/861 ,  H01L21/762 ,  H01L21/3063

CPC classification number: H01L29/7827 ,  H01L21/02233 ,  H01L21/02255 ,  H01L21/26513 ,  H01L21/3063 ,  H01L21/3081 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0665 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/32 ,  H01L29/36 ,  H01L29/41741 ,  H01L29/66128 ,  H01L29/66666 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/8611 ,  H03K17/687

Abstract: A process of forming integrated electronic device having a semiconductor body includes: forming a first electrode region having a first type of conductivity; forming a second electrode region having a second type of conductivity, which forms a junction with the first electrode region; and forming a nanostructured semiconductor region, which extends in one of the first and second electrode regions.