-
公开(公告)号:US20170055345A1
公开(公告)日:2017-02-23
申请号:US15084864
申请日:2016-03-30
Applicant: Samsung Electro-Mechanics Co., Ltd.
Inventor: Sung-Han KIM , Han KIM , Mi-Sun HWANG , Sang-Yul HA , Seok-Hwan AHN , Kyung-Ho LEE
CPC classification number: H05K1/0271 , H05K3/0017 , H05K3/4682 , H05K2201/09781 , H05K2201/098 , H05K2201/2009
Abstract: A printed circuit board and a method of manufacturing the same is provided. The printed circuit board includes an insulating substrate, a circuit disposed on the insulating substrate, a pair of first reinforcements spatially separated in the insulating substrate, the first reinforcements extending parallel to a surface of the insulating substrate, and a second reinforcement configured to connect the pair of first reinforcements.
Abstract translation: 提供一种印刷电路板及其制造方法。 印刷电路板包括绝缘基板,设置在绝缘基板上的电路,在绝缘基板上空间分离的一对第一加强件,平行于绝缘基板的表面延伸的第一加强件,以及第二加强件, 一对第一加强。
-
2.
公开(公告)号:US20160381794A1
公开(公告)日:2016-12-29
申请号:US15196857
申请日:2016-06-29
Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
Inventor: Seok-Hwan AHN , Mi-Sun HWANG , Young-Gwan KO , Jong-Seok BAE , Myung-Sam KANG
CPC classification number: H05K1/0298 , H05K1/0271 , H05K1/09 , H05K1/115 , H05K1/165 , H05K3/007 , H05K3/0076 , H05K3/12 , H05K3/4007 , H05K3/4617 , H05K3/4623 , H05K2201/09136 , H05K2201/09509 , H05K2201/09563 , H05K2201/09672 , H05K2203/043
Abstract: A multilayered substrate includes unit substrates laminated in a direction of thickness thereof, and the unit substrates include a photosensitive insulating layer, a conductive pattern disposed in the photosensitive insulating layer, and a bump penetrating into the photosensitive insulating layer and providing an interlayer connection to the conductive pattern.
Abstract translation: 多层基板包括在其厚度方向上层叠的单位基板,并且单位基板包括光敏绝缘层,设置在感光绝缘层中的导电图案,以及突出到光敏绝缘层中的凸块,并提供到 导电图案。
-
公开(公告)号:US20200178392A1
公开(公告)日:2020-06-04
申请号:US16663419
申请日:2019-10-25
Applicant: Samsung Electro-Mechanics Co., Ltd.
Inventor: Mi-Sun HWANG , Hye-Won JUNG , Jae-Sung SIM , Byung-Duk NA , Hee-Joon CHUN , Sun-A KIM , Deok-Man KANG
Abstract: A printed circuit board includes: an insulating layer having a via hole formed therein; a single layer metal pad disposed in the insulating layer and having a center portion that is exposed by the via hole, the center portion of the pad having a higher roughness than peripheral portions of the pad; and a via formed in the via hole and connected to the center portion of the pad.
-
公开(公告)号:US20200178390A1
公开(公告)日:2020-06-04
申请号:US16676499
申请日:2019-11-07
Applicant: Samsung Electro-Mechanics Co., Ltd.
Inventor: Mi-Sun HWANG , Sun-A KIM
Abstract: A printed circuit board includes an insulating layer, a pad, and a via fill. The insulating layer includes a via hole. The pad is formed in the insulating layer such that an intermediate portion thereof is exposed by the via hole. The pad includes a through hole formed in the intermediate portion. The via fill is formed in the via hole, configured to fill the through hole, and coupled to the intermediate portion.
-
公开(公告)号:US20200170110A1
公开(公告)日:2020-05-28
申请号:US16661051
申请日:2019-10-23
Applicant: Samsung Electro-Mechanics Co., Ltd.
Inventor: Seon-Ha KANG , Sa-Yong LEE , Mi-Sun HWANG , Ju-Ho KIM
Abstract: A printed circuit board is provided. The printed circuit board includes an insulating material, and a circuit comprising a first region that partially penetrates the insulating material, and a second region formed on the first region and that protrudes from an upper portion of the insulating material, the first region includes a first electroplating layer and a first electroless plating layer that are formed between the insulating material and the first electroplating layer.
-
公开(公告)号:US20200154568A1
公开(公告)日:2020-05-14
申请号:US16674507
申请日:2019-11-05
Applicant: Samsung Electro-Mechanics Co., Ltd.
Inventor: Byung-Duk NA , Hye-Won JUNG , Jae-Sung SIM , Mi-Sun HWANG , Hee-Joon CHUN , Deok-Man KANG , Sun-A KIM
Abstract: A printed circuit board including: an insulating material; a metal layer stacked on a surface of the insulating material; and a via hole passing through the metal layer and the insulating material. The metal layer decreases in thickness in a region adjacent to the via hole, and an interface between the insulating material and the metal layer includes a region that is directed toward the via hole.
-
公开(公告)号:US20180070458A1
公开(公告)日:2018-03-08
申请号:US15810343
申请日:2017-11-13
Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
Inventor: Seok-Hwan AHN , Mi-Sun HWANG , Young-Gwan KO , Jong-Seok BAE , Myung-Sam KANG
Abstract: A multilayered substrate in accordance with an aspect of the present disclosure may include an insulating layer, a conductive pattern embedded, at least partially, in the insulating layer, and a bump being electrically connected to the conductive pattern and penetrating the insulating layer. The bump may include a low melting point metal layer having a melting point lower than a melting point of the conductive pattern and a high melting point metal layer having a melting point higher than the melting point of the low melting point metal layer and having a latitudinal cross-sectional area smaller than a latitudinal cross-sectional area of the low melting point metal layer.
-
-
-
-
-
-