公开(公告)号：US20240266309A1

公开(公告)日：2024-08-08

申请号：US18637061

申请日：2024-04-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeonggi Jin ,  Solji Song ,  Taehwa Jeong ,  Jinho Chun ,  Juil Choi ,  Atsushi Fujisaki

IPC: H01L23/00 ,  H01L23/522

CPC classification number: H01L24/14 ,  H01L23/5226 ,  H01L2224/13008 ,  H01L2224/13009 ,  H01L2224/13166 ,  H01L2224/13171 ,  H01L2224/13184 ,  H01L2224/16146

Abstract: A semiconductor package including a semiconductor chip, a redistribution layer structure disposed under the semiconductor chip, a bump pad disposed under the redistribution layer structure and having an upper structure of a first width and a lower structure of a second width less than the first width, a metal seed layer disposed along a lower surface of the upper structure and a side surface of the lower structure, an insulating layer surrounding the redistribution layer structure and the bump pad, and a bump structure disposed under the bump pad. A first undercut is disposed at one end of the metal seed layer that contacts the upper structure, and a second undercut is disposed at an other end of the metal seed layer that contacts the lower

公开(公告)号：US20210035878A1

公开(公告)日：2021-02-04

申请号：US16829227

申请日：2020-03-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeonggi Jin ,  Jumyong Park ,  Jinho An ,  Taehwa Jeong ,  Jinho Chun ,  Juil Choi ,  Atsushi Fujisaki

IPC: H01L23/31 ,  H01L23/29 ,  H01L23/522

Abstract: A semiconductor package includes a semiconductor chip including a chip pad; a lower redistribution structure on the semiconductor chip, the lower redistribution structure including a lower redistribution insulating layer and a lower redistribution pattern electrically connected to the chip pad of the semiconductor chip; a molding layer on at least a portion of the semiconductor chip; and a conductive post in the molding layer, the conductive post having a bottom surface and a top surface, the bottom surface of the conductive post being in contact with the lower redistribution pattern of the lower redistribution structure and the top surface of the conductive post having a concave shape.

公开(公告)号：US11984420B2

公开(公告)日：2024-05-14

申请号：US18074134

申请日：2022-12-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeonggi Jin ,  Solji Song ,  Taehwa Jeong ,  Jinho Chun ,  Juil Choi ,  Atsushi Fujisaki

IPC: H01L23/00 ,  H01L23/522

CPC classification number: H01L24/14 ,  H01L23/5226 ,  H01L2224/13008 ,  H01L2224/13009 ,  H01L2224/13166 ,  H01L2224/13171 ,  H01L2224/13184 ,  H01L2224/16146

Abstract: A semiconductor package including a semiconductor chip, a redistribution layer structure disposed under the semiconductor chip, a bump pad disposed under the redistribution layer structure and having an upper structure of a first width and a lower structure of a second width less than the first width, a metal seed layer disposed along a lower surface of the upper structure and a side surface of the lower structure, an insulating layer surrounding the redistribution layer structure and the bump pad, and a bump structure disposed under the bump pad. A first undercut is disposed at one end of the metal seed layer that contacts the upper structure, and a second undercut is disposed at an other end of the metal seed layer that contacts the lower structure.

公开(公告)号：US20240096851A1

公开(公告)日：2024-03-21

申请号：US18301403

申请日：2023-04-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Unbyoung Kang ,  Jeonggi Jin ,  Gilman Kang ,  Juil Choi ,  Dongchul Han

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/538

CPC classification number: H01L25/0657 ,  H01L23/3107 ,  H01L23/481 ,  H01L23/5389 ,  H01L24/19 ,  H01L2224/12105 ,  H01L2224/32146 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2225/06555

Abstract: A semiconductor package includes a first redistribution structure, a first semiconductor chip on the first redistribution structure and including a first through-electrode, a second semiconductor chip on the first semiconductor chip and including a central portion vertically overlapping the first semiconductor chip and an outer portion horizontally offset from a sidewall of the first semiconductor chip, a molding layer in contact with the first redistribution structure, the first semiconductor chip, and the second semiconductor chip, a second redistribution structure on the second semiconductor chip and the molding layer, a first vertical connection wire extending through the molding layer and extending from the first redistribution structure to the second redistribution structure, and a second vertical connection wire extending through the molding layer and extending from the first redistribution structure to the outer portion of the second semiconductor chip.

公开(公告)号：US20250014958A1

公开(公告)日：2025-01-09

申请号：US18892965

申请日：2024-09-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeonggi Jin ,  Jumyong Park ,  Jinho An ,  Taehwa Jeong ,  Jinho Chun ,  Juil Choi ,  Atsushi Fujisaki

IPC: H01L23/31 ,  H01L23/29 ,  H01L23/522

Abstract: A semiconductor package includes: a lower package including a lower semiconductor chip, a molding layer on a side surface of the lower semiconductor chip, a conductive post in the molding layer and having a concave top surface, a lower redistribution pattern electrically connecting the lower semiconductor chip to the conductive post, and an upper redistribution electrically connected the conductive post; and an upper package on the lower package, the upper package including an upper semiconductor chip. A first portion of an inner wall of the molding layer contacts a sidewall of the conductive post, and a second portion of the inner wall of the molding layer extends vertically above the top surface of the conductive post, wherein the first and second portions of the inner wall of the molding layer are vertically coplanar with each other and with the sidewall of the conductive post.

公开(公告)号：US12021034B2

公开(公告)日：2024-06-25

申请号：US17198359

申请日：2021-03-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Solji Song ,  Byeongchan Kim ,  Jumyong Park ,  Jinho An ,  Chungsun Lee ,  Jeonggi Jin ,  Juil Choi

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/5386 ,  H01L23/5383 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/16227

Abstract: A semiconductor package includes an interposer having a first surface and a second surface opposite to the first surface and including a plurality of bonding pads, and first and second semiconductor devices on the interposer. Each of the plurality of bonding pads includes a first pad pattern provided to be exposed from the first surface and having a first width and a second pad pattern provided on the first pad pattern and having a second width greater than the first width.

公开(公告)号：US11978688B2

公开(公告)日：2024-05-07

申请号：US17966864

申请日：2022-10-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jumyong Park ,  Solji Song ,  Jinho An ,  Jeonggi Jin ,  Jinho Chun ,  Juil Choi

IPC: H01L29/40 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L21/3105 ,  H01L21/321 ,  H01L23/29

CPC classification number: H01L23/3192 ,  H01L21/76898 ,  H01L23/3171 ,  H01L23/481 ,  H01L24/05 ,  H01L21/31053 ,  H01L21/3212 ,  H01L23/293 ,  H01L2224/05025 ,  H01L2224/05073 ,  H01L2224/0557 ,  H01L2224/05573

Abstract: A semiconductor device is disclosed. The semiconductor device includes a via passivation layer disposed on an inactive surface of a substrate, a through-electrode vertically penetrating the substrate and the via passivation layer, a concave portion formed in the top surface of the via passivation layer and disposed adjacent to the through-electrode, and a via protective layer coplanar with the via passivation layer and the through-electrode and to fill the concave portion. In a horizontal cross-sectional view, the via protective layer has a band shape surrounding the through-electrode.

公开(公告)号：US20230361046A1

公开(公告)日：2023-11-09

申请号：US18095642

申请日：2023-01-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juil Choi ,  Jusuk Kang ,  Hyungjun Park ,  Sanghyuck Oh ,  Hyunju Lee ,  Sangyeol Choi

IPC: H01L23/538 ,  H01L23/498 ,  H01L23/31 ,  H10B80/00

CPC classification number: H01L23/5383 ,  H01L23/49811 ,  H01L23/3128 ,  H01L23/49816 ,  H10B80/00

Abstract: Provided are a semiconductor package having a structure maximizing heat dissipation efficiency and a method of manufacturing the same. The semiconductor package includes a first redistribution substrate, a first semiconductor chip on the first redistribution substrate, a plurality of through posts on the first redistribution substrate, around the first semiconductor chip, and a second redistribution substrate located over the first semiconductor chip and the through posts, wherein a top surface of the first semiconductor chip is in contact with a bottom surface of the second redistribution substrate.

公开(公告)号：US20250062213A1

公开(公告)日：2025-02-20

申请号：US18731988

申请日：2024-06-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gyuho Kang ,  Hyungjun Park ,  Kwangok Jeong ,  Juil Choi ,  Taeoh Ha ,  Hongseo Heo

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00

Abstract: A semiconductor package includes a lower redistribution wiring layer that includes first redistribution wirings, a protective layer that defines openings, and bonding pads that are on the protective layer and are electrically connected to the first redistribution wirings through the openings; conductive bumps that are on first bonding pads of the bonding pads; and a semiconductor chip on the first bonding pads, where each of the bonding pads includes: a conductive pillar in a respective opening of the openings of the protective layer, where the conductive pillar includes a first diameter; and a pad pattern that is on the protective layer and an upper surface of the conductive pillar, where the pad pattern includes a second diameter that is greater than the first diameter.

公开(公告)号：US12176313B2

公开(公告)日：2024-12-24

申请号：US17652782

申请日：2022-02-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyoungjoo Lee ,  Unbyoung Kang ,  Sechul Park ,  Sangsick Park ,  Hyojin Yun ,  Teakhoon Lee ,  Juil Choi

IPC: H01L23/00 ,  H01L25/065

Abstract: A semiconductor package includes: a first semiconductor chip; a second semiconductor chip stacked on the first semiconductor chip; an underfill material layer interposed between the first semiconductor chip and the second semiconductor chip; and a first dam structure disposed on the first semiconductor chip. The first dam structure extends along an edge of the second semiconductor chip and includes unit dam structures apart from each other with a slit therebetween. A vertical level of an upper surface of the first dam structure is located between a vertical level of a lower surface of the second semiconductor chip and a vertical level of an upper surface of the second semiconductor chip. A first sidewall of the first dam structure is in contact with the underfill material layer and includes a flat surface parallel to a sidewall of the second semiconductor chip that faces the first sidewall of the first dam structure.