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公开(公告)号:US10825889B2
公开(公告)日:2020-11-03
申请号:US16012997
申请日:2018-06-20
Applicant: Samsung Electronics Co., Ltd.
Inventor: Sang Yeol Kang , Kyu Ho Cho , Han Jin Lim , Cheol Seong Hwang
IPC: H01L49/02 , H01L27/108
Abstract: A semiconductor device including a switching element on a substrate, a pad isolation layer on the switching element, a conductive pad passing through the pad isolation layer and connected to the switching element, an insulating pattern on the pad isolation layer and having a height greater than a horizontal width, a lower electrode on side surfaces of the insulating pattern on side surfaces of the insulating pattern and in contact with the conductive pad, a capacitor dielectric layer on the lower electrode and having a monocrystalline dielectric layer and a polycrystalline dielectric layer, the monocrystalline dielectric layer being relatively close to side surfaces of the insulating pattern compared to the polycrystalline dielectric layer an upper electrode on the capacitor dielectric layer may be provided.
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公开(公告)号:US20200286985A1
公开(公告)日:2020-09-10
申请号:US16590565
申请日:2019-10-02
Applicant: Samsung Electronics Co., Ltd.
Inventor: Han Jin Lim , Ki Nam Kim , Hyung Suk Jung , Kyoo Ho Jung , Ki Hyun Hwang
IPC: H01L49/02 , H01L21/02 , H01L21/28 , H01L27/11507
Abstract: There is provided a semiconductor device capable of improving the performance and/or reliability of the element, by increasing the capacitance of the capacitor, using a capacitor dielectric film including a ferroelectric material and a paraelectric material. The semiconductor device includes first and second electrodes disposed to be spaced apart from each other, and a capacitor dielectric film disposed between the first electrode and the second electrode and including a first dielectric film and a second dielectric film. The first dielectric film includes one of a first monometal oxide film and a first bimetal oxide film, the first dielectric film has an orthorhombic crystal system, the second dielectric film includes a paraelectric material, and a dielectric constant of the capacitor dielectric film is greater than a dielectric constant of the second dielectric film.
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公开(公告)号:US10325992B2
公开(公告)日:2019-06-18
申请号:US14854272
申请日:2015-09-15
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Eunae Cho , Dongjin Lee , Ji Eun Lee , Kyoung-Ho Jung , Dong Su Ko , Yongsu Kim , Jiho Yoo , Sung Heo , Hyun Park , Satoru Yamada , Moonyoung Jeong , Sungjin Kim , Gyeongsu Park , Han Jin Lim
IPC: H01L29/423 , H01L29/49 , H01L21/28 , H01L29/51
Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate including a trench. The semiconductor device further includes a gate electrode disposed in the trench, and a gate insulating film disposed between the substrate and the gate electrode. The gate electrode includes a gate conductor and a metal element, and an effective work function of the gate electrode is less than an effective work function of the gate conductor.
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公开(公告)号:US12230667B2
公开(公告)日:2025-02-18
申请号:US17854679
申请日:2022-06-30
Inventor: Sang Yeol Kang , Kyu Ho Cho , Han Jin Lim , Cheol Seong Hwang
Abstract: A semiconductor device including a switching element on a substrate, a pad isolation layer on the switching element, a conductive pad passing through the pad isolation layer and connected to the switching element, an insulating pattern on the pad isolation layer and having a height greater than a horizontal width, a lower electrode on side surfaces of the insulating pattern on side surfaces of the insulating pattern and in contact with the conductive pad, a capacitor dielectric layer on the lower electrode and having a monocrystalline dielectric layer and a polycrystalline dielectric layer, the monocrystalline dielectric layer being relatively close to side surfaces of the insulating pattern compared to the polycrystalline dielectric layer an upper electrode on the capacitor dielectric layer may be provided.
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公开(公告)号:US11728372B2
公开(公告)日:2023-08-15
申请号:US17714259
申请日:2022-04-06
Applicant: Samsung Electronics Co., Ltd.
Inventor: Han Jin Lim , Ki Nam Kim , Hyung Suk Jung , Kyoo Ho Jung , Ki Hyun Hwang
CPC classification number: H01L28/56 , H01L21/02181 , H01L21/02189 , H01L21/02192 , H01L21/02197 , H01L21/28247 , H10B53/30 , H10B12/00
Abstract: There is provided a semiconductor device capable of improving the performance and/or reliability of the element, by increasing the capacitance of the capacitor, using a capacitor dielectric film including a ferroelectric material and a paraelectric material. The semiconductor device includes first and second electrodes disposed to be spaced apart from each other, and a capacitor dielectric film disposed between the first electrode and the second electrode and including a first dielectric film and a second dielectric film. The first dielectric film includes one of a first monometal oxide film and a first bimetal oxide film, the first dielectric film has an orthorhombic crystal system, the second dielectric film includes a paraelectric material, and a dielectric constant of the capacitor dielectric film is greater than a dielectric constant of the second dielectric film.
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公开(公告)号:US11411069B2
公开(公告)日:2022-08-09
申请号:US17030678
申请日:2020-09-24
Applicant: Samsung Electronics Co., Ltd.
Inventor: Sang Yeol Kang , Kyu Ho Cho , Han Jin Lim , Cheol Seong Hwang
IPC: H01L49/02 , H01L27/108
Abstract: A semiconductor device including a switching element on a substrate, a pad isolation layer on the switching element, a conductive pad passing through the pad isolation layer and connected to the switching element, an insulating pattern on the pad isolation layer and having a height greater than a horizontal width, a lower electrode on side surfaces of the insulating pattern on side surfaces of the insulating pattern and in contact with the conductive pad, a capacitor dielectric layer on the lower electrode and having a monocrystalline dielectric layer and a polycrystalline dielectric layer, the monocrystalline dielectric layer being relatively close to side surfaces of the insulating pattern compared to the polycrystalline dielectric layer an upper electrode on the capacitor dielectric layer may be provided.
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公开(公告)号:US20210376099A1
公开(公告)日:2021-12-02
申请号:US17400901
申请日:2021-08-12
Applicant: Samsung Electronics Co., Ltd.
Inventor: Eunae Cho , Dongjin Lee , Ji Eun Lee , Kyoung-Ho Jung , Dong Su Ko , Yongsu Kim , Jiho Yoo , Sung Heo , Hyun Park , Satoru Yamada , Moonyoung Jeong , Sungjin Kim , Gyeongsu Park , Han Jin Lim
IPC: H01L29/423 , H01L29/49 , H01L21/28 , H01L29/51
Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate including a trench. The semiconductor device further includes a gate electrode disposed in the trench, and a gate insulating film disposed between the substrate and the gate electrode. The gate electrode includes a gate conductor and a metal element, and an effective work function of the gate electrode is less than an effective work function of the gate conductor.
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公开(公告)号:US20190312119A1
公开(公告)日:2019-10-10
申请号:US16432298
申请日:2019-06-05
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Eunae CHO , Dongjin Lee , Ji Eun Lee , Kyoung-Ho Jung , Dong Su Ko , Yongsu Kim , Jiho Yoo , Sung Heo , Hyun Park , Satoru Yamada , Moonyoung Jeong , Sungjin Kim , Gyeongsu Park , Han Jin Lim
IPC: H01L29/423 , H01L29/51 , H01L29/49 , H01L21/28
Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate including a trench. The semiconductor device further includes a gate electrode disposed in the trench, and a gate insulating film disposed between the substrate and the gate electrode. The gate electrode includes a gate conductor and a metal element, and an effective work function of the gate electrode is less than an effective work function of the gate conductor.
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公开(公告)号:US20240357796A1
公开(公告)日:2024-10-24
申请号:US18543261
申请日:2023-12-18
Applicant: Samsung Electronics Co., Ltd.
Inventor: Han Jin Lim , Jin Woo Han , Ki Seok Lee
CPC classification number: H10B12/377 , H01L28/55 , H10B12/36 , H10B12/50 , H10B53/30
Abstract: Provided is a semiconductor memory device. The semiconductor memory device includes a substrate, a channel region on the substrate, first and second source/drain regions electrically connected to the channel region, a gate electrode that extends in a first direction and is on the channel region, a conductive line that extends in a second direction intersecting the first direction and is electrically connected to the second source/drain region, and a capacitor structure electrically connected to the first source/drain region on the substrate. The capacitor structure may include a plurality of first electrodes stacked and spaced apart from each other in a third direction perpendicular to an upper surface of the substrate, a plurality of trenches extending into the plurality of first electrodes, a capacitor dielectric film that extends along side walls of each of the plurality of trenches, and a plurality of second electrodes in the plurality of trenches, respectively.
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公开(公告)号:US11737277B2
公开(公告)日:2023-08-22
申请号:US17523014
申请日:2021-11-10
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Ji Hoon Choi , Sung Gil Kim , Seulye Kim , Jung Ho Kim , Hong Suk Kim , Phil Ouk Nam , Jae Young Ahn , Han Jin Lim
IPC: H10B43/27 , H10B43/10 , H01L23/528
CPC classification number: H10B43/27 , H01L23/5283 , H10B43/10
Abstract: A semiconductor device includes a stack structure on a substrate, the stack structure including interlayer insulating layers and first gate electrodes alternately stacked on each other, a semiconductor layer in an opening penetrating through the stack structure, a first dielectric layer between the semiconductor layer and the stack structure, and a lower pattern closer to the substrate than to the first gate electrodes in the stack structure, the lower pattern including a first surface facing the first dielectric layer, and a second surface facing the stack structure, the second surface defining an acute angle with the first surface, wherein the first dielectric layer includes a first portion facing the stack structure, and a second portion facing the first surface of the lower pattern, the second portion having a thickness greater than a thickness of the first portion.
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