公开(公告)号：US09053774B2

公开(公告)日：2015-06-09

申请号：US14066193

申请日：2013-10-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ho-Seok Seol ,  Seung-Jun Bae ,  Ho-Sung Song

IPC: G11C7/00 ,  G11C8/18 ,  H03K5/156 ,  G11C29/02

CPC classification number: G11C8/18 ,  G11C29/023 ,  G11C29/028 ,  H03K5/1565

Abstract: A duty cycle corrector includes a sensing unit, a pad unit, a fuse unit, and a driver unit. The sensing unit generates at least one sensing signal based on the sensed duty cycle ratio of an output signal. The pad unit outputs at least one decision signal based on the at least one sensing signal. The fuse unit generates a duty cycle control signal based on at least one received fuse control signal. The driver unit adjusts a duty cycle ratio of an input signal to generate the output signal based on the duty cycle control signal. The driver unit adjusts the duty cycle ratio of the input signal by adjusting a pull-up strength or a pull-down strength of the input signal based on the duty cycle control signal.

Abstract translation: 占空比校正器包括感测单元，衬垫单元，保险丝单元和驱动单元。 感测单元基于感测到的输出信号的占空比来产生至少一个感测信号。 垫单元基于至少一个感测信号输出至少一个判定信号。 熔丝单元基于至少一个接收的熔丝控制信号产生占空比控制信号。 驱动单元根据占空比控制信号来调整输入信号的占空比，生成输出信号。 驱动器单元通过基于占空比控制信号调整输入信号的上拉强度或下拉强度来调节输入信号的占空比。

公开(公告)号：US09264039B2

公开(公告)日：2016-02-16

申请号：US14202323

申请日：2014-03-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ho-Seok Seol ,  Seung-Jun Bae ,  Young-Soo Sohn ,  Ho-Sung Song

IPC: H03K17/16 ,  H03K19/003 ,  H03K19/00

CPC classification number: H03K19/0005

Abstract: An on-die termination (ODT) circuit includes a calibration unit, an offset-code generating unit, an adder, and an ODT unit. The calibration unit generates a pull-up code and a pull-down code. The offset-code generates a pull-up offset code and a pull-down offset code based on a mode-register-set signal, the pull-up code, and the pull-down code. The adder adds the pull-up offset code and the pull-down offset code to the pull-up code and the pull-down code, respectively, and generates a pull-up calibration code and a pull-down calibration code. The ODT unit changes ODT resistance in response to the pull-up calibration code and the pull-down calibration code.

Abstract translation: 片上终端（ODT）电路包括校准单元，偏移码生成单元，加法器和ODT单元。 校准单元生成一个上拉代码和一个下拉代码。 偏移码基于模式寄存器设置信号，上拉代码和下拉码产生上拉偏移码和下拉偏移码。 加法器分别将上拉偏移代码和下拉偏移代码加到上拉代码和下拉代码，并产生一个上拉校准代码和一个下拉校准代码。 ODT单元根据上拉校准代码和下拉校准代码改变ODT电阻。

公开(公告)号：US09824946B2

公开(公告)日：2017-11-21

申请号：US15231862

申请日：2016-08-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Yong Byun ,  Ho-Sung Song ,  Chi-Wook Kim

IPC: H01L21/66 ,  H01L21/78 ,  H01L23/544 ,  G01R31/28

CPC classification number: H01L22/34 ,  G01R31/2834 ,  G01R31/2856 ,  G01R31/2884 ,  G01R31/2894 ,  G01R31/31713 ,  G01R31/318511 ,  H01L21/78 ,  H01L22/14 ,  H01L22/32 ,  H01L23/544 ,  H01L2223/5446 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012

Abstract: A method of manufacturing a semiconductor chip from a wafer having a test architecture includes forming a plurality of dies on a wafer, each of the plurality of dies including a semiconductor device, forming at least two common pads commonly coupled to the dies, the at least two common pads being formed in a scribe lane, the scribe lane distinguishing the dies with respect to each other, and simultaneously testing the semiconductor devices at a wafer level, using the at least two common pads.

公开(公告)号：US09461656B2

公开(公告)日：2016-10-04

申请号：US14558072

申请日：2014-12-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hye-Yoon Joo ,  Seung-Jun Bae ,  Young-Soo Sohn ,  Ho-Sung Song ,  Jeong-Don Ihm

IPC: H03L7/06 ,  H03L7/087 ,  H03L7/07 ,  H03L7/083 ,  H03L7/099 ,  G11C7/22

CPC classification number: H03L7/087 ,  G11C7/222 ,  H03L7/07 ,  H03L7/083 ,  H03L7/0995

Abstract: An injection-locked phase-locked loop (ILPLL) circuit includes a delay-locked loop (DLL) and an ILPLL. The DLL is configured to generate a DLL clock by performing a delay-locked operation on a reference clock. The ILPLL includes a voltage-controlled oscillator (VCO), and is configured to generate an output clock by performing an injection synchronous phase-locked operation on the reference clock. The DLL clock is injected into the VCO as an injection clock of the VCO.

Abstract translation: 注射锁相环（ILPLL）电路包括延迟锁定环（DLL）和ILPLL。 DLL被配置为通过对参考时钟执行延迟锁定操作来生成DLL时钟。 ILPLL包括压控振荡器（VCO），并且被配置为通过对参考时钟执行注入同步锁相操作来产生输出时钟。 将DLL时钟作为VCO的注入时钟注入到VCO中。

公开(公告)号：US10163741B2

公开(公告)日：2018-12-25

申请号：US15677053

申请日：2017-08-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young-Ho Kim ,  Ho-Sung Song ,  Jeong-Sik Nam ,  Kyoung-Min Kim ,  Tae-Hyeong Lee

IPC: G01R31/28 ,  H01L21/66 ,  H01L21/78 ,  H01L23/544

Abstract: A semiconductor device structure, including integrated circuits of semiconductor chips and scribe lanes between the regions in which the circuits have been formed, has at least one redistribution pad disposed in one of the scribe lanes for simultaneously testing a group of the integrated circuits, and a metal interconnection structure disposed beneath the redistribution pad(s). The metal interconnection structure includes at least conductive via contacting the redistribution pad at the bottom of the pad. The conductive via(s) is/are arranged so that at least a portion of each via remains attached to the redistribution pad when the structure is sawed along the scribe lane.