公开(公告)号：US10886255B2

公开(公告)日：2021-01-05

申请号：US16532598

申请日：2019-08-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-Seok Hong ,  Ji-Hoon Kim ,  Tae-Hun Kim ,  Hyuek-Jae Lee ,  Ji-Hwan Hwang

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L23/48 ,  H01L21/56 ,  H01L21/822

Abstract: A die stack structure may include a base die having base contact pads insulated by a base protection patterns and a flat side surface, a die stack bonded to the base die and having a plurality of component dies on the base die such that each of the component dies includes component contact pads insulated by a corresponding component protection pattern, and a residual mold unevenly arranged on a side surface of the die stack such that the component dies are attached to each other by the residual mold.

公开(公告)号：US20170330767A1

公开(公告)日：2017-11-16

申请号：US15586716

申请日：2017-05-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Un-Byoung Kang ,  Tae-Je CHO ,  Hyuek-Jae Lee ,  Cha-Jea Jo

IPC: H01L21/48 ,  C23C14/58 ,  C23C14/34 ,  C23C14/20 ,  C23C14/06 ,  C23C14/04 ,  C23C14/02 ,  B05D7/00 ,  B05D3/02 ,  B05D1/38 ,  B05D1/32 ,  B05D1/00

CPC classification number: H01L21/4857 ,  B05D1/005 ,  B05D1/32 ,  B05D1/38 ,  B05D3/0209 ,  B05D7/546 ,  C23C14/024 ,  C23C14/046 ,  C23C14/0641 ,  C23C14/205 ,  C23C14/34 ,  C23C14/588 ,  C23C18/00 ,  C23C18/38 ,  H01L21/486 ,  H01L23/4334 ,  H01L23/473 ,  H01L23/49822 ,  H01L23/5385 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L24/81 ,  H01L25/03 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/13111 ,  H01L2224/16227 ,  H01L2224/73253 ,  H01L2224/81005 ,  H01L2224/97 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1437 ,  H01L2924/15311 ,  H01L2924/18161 ,  H05K3/465 ,  H05K3/4682 ,  H05K2201/10378 ,  H05K2203/025 ,  H05K2203/0588 ,  H01L2924/01047 ,  H01L2224/81

Abstract: A method of fabricating an interposer includes: providing a carrier substrate; forming a unit redistribution layer on the carrier substrate, the unit redistribution layer including a conductive via plug and a conductive redistribution line; and removing the carrier substrate from the unit redistribution layer. The formation of the unit redistribution layer includes: forming a first photosensitive pattern layer including a first via hole pattern; forming a second photosensitive pattern layer including a second via hole pattern and a redistribution pattern on the first photosensitive pattern layer; at least partially filling insides of the first via hole pattern, the second via hole pattern, and the redistribution pattern with a conductive material; and performing planarization to make a top surface of the unit redistribution layer flat. According to the method, no undercut occurs under a conductive structure and there are no bubbles between adjacent conductive structures, thus device reliability is enhanced and pattern accuracy is realized.

公开(公告)号：US10535534B2

公开(公告)日：2020-01-14

申请号：US15586716

申请日：2017-05-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Un-Byoung Kang ,  Tae-Je Cho ,  Hyuek-Jae Lee ,  Cha-Jea Jo

IPC: H01L21/48 ,  H05K3/46 ,  C23C18/00 ,  H01L23/433 ,  H01L23/498 ,  B05D1/00 ,  B05D1/32 ,  B05D1/38 ,  B05D3/02 ,  B05D7/00 ,  C23C14/02 ,  C23C14/04 ,  C23C14/06 ,  C23C14/20 ,  C23C14/34 ,  C23C14/58 ,  C23C18/38 ,  H01L23/00 ,  H01L25/03 ,  H01L23/473 ,  H01L23/538 ,  H01L25/065

Abstract: A method of fabricating an interposer includes: providing a carrier substrate; forming a unit redistribution layer on the carrier substrate, the unit redistribution layer including a conductive via plug and a conductive redistribution line; and removing the carrier substrate from the unit redistribution layer. The formation of the unit redistribution layer includes: forming a first photosensitive pattern layer including a first via hole pattern; forming a second photosensitive pattern layer including a second via hole pattern and a redistribution pattern on the first photosensitive pattern layer; at least partially filling insides of the first via hole pattern, the second via hole pattern, and the redistribution pattern with a conductive material; and performing planarization to make a top surface of the unit redistribution layer flat. According to the method, no undercut occurs under a conductive structure and there are no bubbles between adjacent conductive structures, thus device reliability is enhanced and pattern accuracy is realized.

公开(公告)号：US11018026B2

公开(公告)日：2021-05-25

申请号：US16699283

申请日：2019-11-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Un-Byoung Kang ,  Tae-Je Cho ,  Hyuek-Jae Lee ,  Cha-Jea Jo

IPC: H05K1/11 ,  H05K1/18 ,  H01L21/48 ,  H05K3/46 ,  C23C18/00 ,  H01L23/433 ,  H01L23/498 ,  B05D1/00 ,  B05D1/32 ,  B05D1/38 ,  B05D3/02 ,  B05D7/00 ,  C23C14/02 ,  C23C14/04 ,  C23C14/06 ,  C23C14/20 ,  C23C14/34 ,  C23C14/58 ,  C23C18/38 ,  H01L23/00 ,  H01L25/03 ,  H01L23/473 ,  H01L23/538 ,  H01L25/065 ,  H05K1/14

Abstract: A semiconductor package includes: a plurality of unit redistribution layers vertically stacked, each including: a first polymer layer having a first via hole pattern; a second polymer layer formed on the first polymer layer, and having a redistribution pattern on the first polymer layer and a second via hole pattern in the first via hole pattern; a seed layer covering sidewalls and bottom surfaces of the redistribution pattern and the second via hole pattern; a conductive via plug formed in the second via hole pattern; and a conductive redistribution line formed in the redistribution pattern; a connection terminal disposed on a bottom surface of a lowermost unit redistribution layer and electrically connected to the conductive via plug; a semiconductor device mounted on the unit redistribution layers with a conductive terminal interposed therebetween. Upper surfaces of the second polymer layer, the conductive redistribution line and the conductive via plug are substantially coplanar.