-
公开(公告)号：US20220130801A1
公开(公告)日：2022-04-28
申请号：US17568558
申请日：2022-01-04
发明人： Hyuekjae LEE , Jihoon KIM , Jihwan SUH , Soyoun LEE , Jiseok HONG , Taehun KIM , Jihwan HWANG
IPC分类号： H01L25/065 , H01L23/00 , H01L23/538 , H01L23/31 , H01L23/16
摘要： Provided is a semiconductor package including a semiconductor stack including a first lower chip, a second lower chip, a gap filler disposed between the first lower chip and the second lower chip, and a first upper chip disposed on an upper surface of the first lower chip, an upper surface of the second lower chip, and an upper surface of the gap filler, the first lower chip includes first upper surface pads and a first upper surface dielectric layer, the second lower chip includes second upper surface pads and a second upper surface dielectric layer, the first upper chip includes lower surface pads and a lower surface dielectric layer, and an area of an upper surface of each of the second upper surface pads is greater than an area of a lower surface of each of the lower surface pads.
-
公开(公告)号：US20220139874A1
公开(公告)日：2022-05-05
申请号：US17364541
申请日：2021-06-30
发明人： Sanghoon LEE , Hyuekjae LEE
IPC分类号： H01L25/065 , H01L23/498 , H01L23/538 , H01L23/00 , H01L23/48
摘要： A semiconductor package including a first semiconductor chip including a first semiconductor layer having a first forward surface having a first integrated circuit thereon and a first rear surface and a plurality of first through vias electrically connected to the first integrated circuit and including at least first and second groups of first through vias, a second semiconductor chip including a second integrated circuit electrically connected to the first group of first through vias, and a third semiconductor chip including third through vias electrically connected to the second group of first through vias, wherein the first group of first through vias transfer input/output signals of the first integrated circuit, and the second group of first through vias transfer power to the first integrated circuit, may be provided.
-
公开(公告)号：US20210151410A1
公开(公告)日：2021-05-20
申请号：US17036508
申请日：2020-09-29
发明人： Jihwan HWANG , Taehun KIM , Jihwan SUH , Soyoun LEE , Hyuekjae LEE , Jiseok HONG
IPC分类号： H01L25/065 , H01L25/00
摘要： A semiconductor package and a method of forming the same are provided. The semiconductor package includes one or a plurality of chips on a substrate, bumps disposed below each of the one or plurality of chips, an underfill material layer on the substrate, on a side surface of each of the bumps, and extending to side surfaces of the one or plurality of chips, and a mold layer on the substrate and contacting the underfill material layer. The underfill material layer includes a first side portion, a second side portion on the first side portion and having a slope, steeper than a slope of the first side portion, and a third side portion on the second side portion and having a slope that is less steep than a slope of the second side portion.
-
公开(公告)号：US20210028152A1
公开(公告)日：2021-01-28
申请号：US16833761
申请日：2020-03-30
发明人： Hyuekjae LEE , Jihoon KIM , Jihwan SUH , Soyoun LEE , Jiseok HONG , Taehun KIM , Jihwan HWANG
IPC分类号： H01L25/065 , H01L23/00 , H01L23/16 , H01L23/31 , H01L23/538
摘要： Provided is a semiconductor package including a semiconductor stack including a first lower chip, a second lower chip, a gap filler disposed between the first lower chip and the second lower chip, and a first upper chip disposed on an upper surface of the first lower chip, an upper surface of the second lower chip, and an upper surface of the gap filler, the first lower chip includes first upper surface pads and a first upper surface dielectric layer, the second lower chip includes second upper surface pads and a second upper surface dielectric layer, the first upper chip includes lower surface pads and a lower surface dielectric layer, and an area of an upper surface of each of the second upper surface pads is greater than an area of a lower surface of each of the lower surface pads.
-
公开(公告)号：US20240258278A1
公开(公告)日：2024-08-01
申请号：US18500089
申请日：2023-11-01
发明人： Hyungchul SHIN , Won IL LEE , Hyuekjae LEE , Enbin JO
IPC分类号： H01L25/065 , H01L23/00 , H01L25/18 , H10B80/00
CPC分类号： H01L25/0657 , H01L24/05 , H01L24/06 , H01L24/08 , H01L25/18 , H10B80/00 , H01L24/13 , H01L24/16 , H01L2224/05552 , H01L2224/0557 , H01L2224/05647 , H01L2224/0603 , H01L2224/06181 , H01L2224/08145 , H01L2224/08225 , H01L2224/13109 , H01L2224/13111 , H01L2224/13113 , H01L2224/13117 , H01L2224/1312 , H01L2224/13139 , H01L2224/13147 , H01L2224/13155 , H01L2224/16227 , H01L2225/06544 , H01L2225/06562 , H01L2225/06565 , H01L2924/01058 , H01L2924/1431 , H01L2924/1432 , H01L2924/1433
摘要： A semiconductor package includes a lower semiconductor chip, a first semiconductor chip, a first through-electrode vertically penetrating the first semiconductor substrate, a first upper pad connected to the first through electrode, a first circuit layer disposed on the lower surface of the first semiconductor substrate, and a first lower pad disposed on a lower surface of the first circuit layer. A second semiconductor chip includes a second through-electrode spaced apart from the first through-electrode and vertically penetrating the second semiconductor substrate. A second upper pad is connected to the second through electrode. A second circuit layer is disposed on the lower surface of the second semiconductor substrate, and a second lower pad is connected to the second through-electrode on the lower surface of the second circuit layer through the second circuit layer and is integrally formed with the first upper pad.
-
公开(公告)号：US20230317654A1
公开(公告)日：2023-10-05
申请号：US17980740
申请日：2022-11-04
发明人： Jihoon KIM , Minki KIM , Wonil LEE , Hyuekjae LEE
IPC分类号： H01L23/00 , H01L25/065 , H01L25/18 , H01L25/00
CPC分类号： H01L24/08 , H01L25/0657 , H01L25/18 , H01L24/05 , H01L24/80 , H01L25/50 , H01L2224/05013 , H01L2224/05015 , H01L2224/05017 , H01L2224/05147 , H01L2224/08145 , H01L2224/80031 , H01L2224/80895 , H01L2224/80896 , H01L2924/1431 , H01L2924/14511
摘要： Disclosed are semiconductor devices and their fabrication methods. The semiconductor device comprises lower and upper structures. The lower structure includes a first semiconductor substrate, a first pad, and a first dielectric layer. The upper structure includes a second semiconductor substrate, a second pad, and a second dielectric layer. The upper and lower structures are bonded to each other to allow the first and second pads to come into contact each other and to allow the first and second dielectric layers to come into contact each other. A first interface between the first and second pads is at a level different from that of a second interface between the first and second dielectric layers. A first area of the first pad is greater than a second area of the second pad. A second thickness of the second pad is different from a first thickness of the first pad.
-
公开(公告)号：US20220344308A1
公开(公告)日：2022-10-27
申请号：US17861580
申请日：2022-07-11
发明人： Jihwan HWANG , Taehun KIM , Jihwan SUH , Soyoun LEE , Hyuekjae LEE , Jiseok HONG
IPC分类号： H01L25/065 , H01L25/00
摘要： A semiconductor package and a method of forming the same are provided. The semiconductor package includes one or a plurality of chips on a substrate, bumps disposed below each of the one or plurality of chips, an underfill material layer on the substrate, on a side surface of each of the bumps, and extending to side surfaces of the one or plurality of chips, and a mold layer on the substrate and contacting the underfill material layer. The underfill material layer includes a first side portion, a second side portion on the first side portion and having a slope, steeper than a slope of the first side portion, and a third side portion on the second side portion and having a slope that is less steep than a slope of the second side portion.
-
-
-
-
-
-
搜索结果
7 条记录 (耗时 0.025 秒)
