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    Semiconductor device including vertical channel layer
    1.
    发明授权
    Semiconductor device including vertical channel layer 有权

    公开(公告)号：US10854630B2

    公开(公告)日：2020-12-01

    申请号：US16526139

    申请日：2019-07-30

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kwang-soo Kim ,  Yong-seok Kim ,  Tae-hun Kim ,  Min-kyung Bae ,  Jae-hoon Jang ,  Kohji Kanamori

    IPC: H01L27/11582 ,  H01L29/08 ,  H01L29/78 ,  H01L27/11565

    Abstract: A semiconductor device includes a plurality of channel structures on a substrate, each channel structure extending in a first direction perpendicular to the substrate, a common source extension structure including a first semiconductor layer having an n-type conductivity and a gate insulating layer between the substrate and the channel structures, a plurality of gate electrodes on the common source extension structure and spaced apart from each other on a sidewall of each of the channel structures in the first direction, and a common source region on the substrate in contact with the common source extension structure and including a second semiconductor layer having an n-type conductivity. An upper portion of the common source extension structure has a first width, and a lower portion of the common source extension structure has a second width smaller than the first width.

    VERTICAL NON-VOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME
    4.
    发明申请
    VERTICAL NON-VOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME 审中-公开
    垂直非易失性存储器件及其制造方法

    公开(公告)号：US20130279233A1

    公开(公告)日：2013-10-24

    申请号：US13921554

    申请日：2013-06-19

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sung-min Hwang ,  Han-soo Kim ,  Won-seok CHO ,  Jae-hoon Jang ,  Sun-il Shim ,  Jae-hun Jeong ,  Ki-hyun Kim

    IPC: G11C5/06

    CPC classification number: G11C5/06 ,  H01L23/5283 ,  H01L27/112 ,  H01L27/115 ,  H01L27/11517

    Abstract: A vertical non-volatile memory device is structured/fabricated to include a substrate, groups of memory cell strings each having a plurality of memory transistors distributed vertically so that the memory throughout multiple layers on the substrate, integrated word lines coupled to sets of the memory transistors, respectively, and stacks of word select lines. The memory transistors of each set are those transistors, of one group of the memory cell strings, which are disposed in the same layer above the substrate. The word select lines are respectively connected to the integrated word lines.

    Abstract translation: 垂直非易失性存储器件被构造/制造成包括衬底，每组具有多个垂直分布的存储器晶体管的存储单元串组，使得衬底上多层的存储器，与存储器组合耦合的集成字线 晶体管和字选择线的堆叠。 每组的存储晶体管是一组存储单元串的晶体管，它们设置在衬底上方的相同层中。 字选择线分别连接到集成字线。

    Semiconductor device including vertical channel layer
    7.
    发明授权
    Semiconductor device including vertical channel layer 有权

    公开(公告)号：US10411033B2

    公开(公告)日：2019-09-10

    申请号：US15993756

    申请日：2018-05-31

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kwang-soo Kim ,  Yong-seok Kim ,  Tae-hun Kim ,  Min-kyung Bae ,  Jae-hoon Jang ,  Kohji Kanamori

    IPC: H01L27/11582 ,  H01L29/08 ,  H01L29/78

    Abstract: A semiconductor device includes a plurality of channel structures on a substrate, each channel structure extending in a first direction perpendicular to the substrate, and having a gate insulating layer and a channel layer, a common source extension region including a first semiconductor layer having an n-type conductivity between the substrate and the channel structures, a plurality of gate electrodes on the common source extension region and spaced apart from each other on a sidewall of each of the channel structures in the first direction, and a common source region on the substrate in contact with the common source extension region and including a second semiconductor layer having an n-type conductivity, wherein the gate insulating layer of each of the channel structures extends to cover an upper surface and at least a portion of a bottom surface of the common source extension region.

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