公开(公告)号：US09601466B2

公开(公告)日：2017-03-21

申请号：US14725268

申请日：2015-05-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeongwon Yoon ,  Boin Noh ,  Baikwoo Lee ,  Hyunsuk Chun

IPC: H01L23/02 ,  H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05573 ,  H01L2224/05611 ,  H01L2224/05623 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/0566 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/0567 ,  H01L2224/0568 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/06181 ,  H01L2224/11334 ,  H01L2224/11436 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/13018 ,  H01L2224/13076 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13123 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1316 ,  H01L2224/13163 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/13169 ,  H01L2224/1317 ,  H01L2224/1318 ,  H01L2224/13181 ,  H01L2224/13184 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/81191 ,  H01L2224/81205 ,  H01L2224/818 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2924/01004 ,  H01L2924/01014 ,  H01L2924/01032 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/05618

Abstract: Provided is a semiconductor package and a method of making same, including a first package substrate; a first semiconductor chip mounted on the first package substrate and having a first pad and a second pad, wherein the first pad is provided on a top of the first semiconductor chip and the second pad is provided on a bottom of the first semiconductor chip, the bottom being an opposite surface of the top; and a clad metal provided on the first pad and electrically connecting the first semiconductor chip to one of a second semiconductor chip and second package substrate provided on the top of the first semiconductor chip.

公开(公告)号：US20160071824A1

公开(公告)日：2016-03-10

申请号：US14725268

申请日：2015-05-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeongwon Yoon ,  Boin Noh ,  Baikwoo Lee ,  Hyunsuk Chun

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L25/0657 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05573 ,  H01L2224/05611 ,  H01L2224/05623 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/0566 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/0567 ,  H01L2224/0568 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/06181 ,  H01L2224/11334 ,  H01L2224/11436 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/13018 ,  H01L2224/13076 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13123 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1316 ,  H01L2224/13163 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/13169 ,  H01L2224/1317 ,  H01L2224/1318 ,  H01L2224/13181 ,  H01L2224/13184 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/81191 ,  H01L2224/81205 ,  H01L2224/818 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2924/01004 ,  H01L2924/01014 ,  H01L2924/01032 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/05618

Abstract: Provided is a semiconductor package and a method of making same, including a first package substrate; a first semiconductor chip mounted on the first package substrate and having a first pad and a second pad, wherein the first pad is provided on a top of the first semiconductor chip and the second pad is provided on a bottom of the first semiconductor chip, the bottom being an opposite surface of the top; and a clad metal provided on the first pad and electrically connecting the first semiconductor chip to one of a second semiconductor chip and second package substrate provided on the top of the first semiconductor chip.

Abstract translation: 提供一种半导体封装及其制造方法，包括第一封装衬底; 安装在第一封装基板上并具有第一焊盘和第二焊盘的第一半导体芯片，其中第一焊盘设置在第一半导体芯片的顶部上，第二焊盘设置在第一半导体芯片的底部， 底部是顶部的相对表面; 以及设置在所述第一焊盘上并且将所述第一半导体芯片电连接到设置在所述第一半导体芯片的顶部上的第二半导体芯片和第二封装基板中的一个的复合金属。

公开(公告)号：US20230148222A1

公开(公告)日：2023-05-11

申请号：US18050724

申请日：2022-10-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Boin Noh ,  Jeonghoon Ahn

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L21/48

CPC classification number: H01L23/49838 ,  H01L24/08 ,  H01L25/0655 ,  H01L21/486 ,  H01L21/4857 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49894 ,  H01L2224/08225 ,  H01L2924/3511 ,  H01L2924/182 ,  H01L2924/1616 ,  H01L2924/16251 ,  H01L2924/1632

Abstract: An interposer structure includes: an interposer substrate; an interposer through electrode penetrating through the interposer substrate in a vertical direction; a redistribution structure on the interposer substrate and including a redistribution pattern connected to the interposer through electrode and a redistribution insulating layer on side surfaces of the redistribution pattern on the interposer substrate; a conductive post on the redistribution structure and connected to the redistribution pattern; and an interposer insulating layer on side surfaces of the conductive post on the redistribution structure.

公开(公告)号：US11164821B2

公开(公告)日：2021-11-02

申请号：US16853910

申请日：2020-04-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Boin Noh

IPC: H01L23/495 ,  H01L23/538 ,  H01L23/367 ,  H01L23/00 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

Abstract: A semiconductor package including a semiconductor chip having a chip pad thereon; a first insulating layer; a redistribution line pattern on the first insulating layer; a redistribution via pattern through the first insulating layer to connect the chip pad to the redistribution line pattern; a second insulating layer covering the redistribution line pattern and including a first part having a first thickness and a second part having a second thickness. the second part being inward relative to the first part; a first conductive pillar through the first part and connected to the redistribution line pattern; a second conductive pillar through the second part and connected to the redistribution line pattern; a first connection pad on the first conductive pillar; a second connection pad on the second conductive pillar; a first connection terminal contacting the first connection pad; and a second connection terminal contacting the second connection pad.