SEMICONDUCTOR DEVICE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME

    公开(公告)号:US20240413104A1

    公开(公告)日:2024-12-12

    申请号:US18425173

    申请日:2024-01-29

    Abstract: There is provided a semiconductor device with improved product reliability. The semiconductor device includes a substrate, a structure on the substrate and including multilayer metal patterns and multilayer insulating layers, and a pad layer on the structure and including a plurality of bonding pads, wherein a plurality of uppermost patterns at an uppermost layer among the multilayer metal patterns include electrode patterns for transferring signals and alleviation patterns that do not transfer the signals, a first ratio of the alleviation patterns within a first reference shape at a first distance from an edge of the structure is greater than a second ratio of the alleviation patterns within a second reference shape at a second distance from the edge of the structure, and the first distance is greater than the second distance.

    SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING THE SAME

    公开(公告)号:US20250079393A1

    公开(公告)日:2025-03-06

    申请号:US18748354

    申请日:2024-06-20

    Abstract: A semiconductor package includes: a first semiconductor chip including a first substrate and a first through electrode passing through the first substrate, wherein the first substrate has a first active surface and a first non-active surface; a chip structure including a plurality of second semiconductor chips stacked on the first semiconductor chip, wherein each second semiconductor chip includes a second substrate and a second through electrode passing through the second substrate; and a third semiconductor chip disposed on the chip structure, and including a third substrate, wherein the first substrate has a first width and a first thickness, wherein the second substrate has a second width and a second thickness, and the third substrate has a third width and a third thickness, wherein the third thickness is thicker than the second thickness, and the third width is greater than the second width.

    BI-DIRECTIONAL CAMERA MODULE AND FLIP CHIP BONDER INCLUDING THE SAME
    5.
    发明申请
    BI-DIRECTIONAL CAMERA MODULE AND FLIP CHIP BONDER INCLUDING THE SAME 有权
    双向摄像机模块和包括其中的浮动芯片粘合剂

    公开(公告)号:US20130258188A1

    公开(公告)日:2013-10-03

    申请号:US13828618

    申请日:2013-03-14

    Abstract: Bi-directional camera modules and flip chip bonders including the same are provided. The module includes a circuit board on which an upper sensor and a lower sensor are mounted, an upper lens and a lower lens disposed on the upper sensor and under the lower sensor, respectively, and a housing fixing the upper lens and the lower lens spaced apart from the upper sensor and the lower sensor, respectively. The housing surrounds the circuit board. The housing has a plurality of inlets and an outlet through which air flows, and the housing has an air passage connected from the inlets to the outlet via a space between lower lens and the lower sensor.

    Abstract translation: 提供了包括其的双向相机模块和倒装芯片接合器。 模块包括分别安装有上传感器和下传感器的电路板,分别设置在上传感器和下传感器下的上透镜和下透镜,以及固定上透镜和下透镜间隔开的壳体 分别是上传感器和下传感器。 外壳围绕电路板。 壳体具有多个入口和空气流过的出口,并且壳体具有通过下透镜和下传感器之间的空间从入口连接到出口的空气通道。

    SEMICONDUCTOR PACKAGE
    6.
    发明申请

    公开(公告)号:US20220122918A1

    公开(公告)日:2022-04-21

    申请号:US17492788

    申请日:2021-10-04

    Abstract: A semiconductor package includes a first semiconductor chip having a first face and a second face opposite thereto. The first semiconductor chip includes a first wiring layer having a surface that forms the first face. A second semiconductor chip disposed on the first face of the first semiconductor chip includes a second wiring layer directly contacting the first wiring layer. A first mold layer is disposed on one lateral side of the first semiconductor chip and directly contacts the second wiring layer. A first via penetrates the first mold layer. A width of the first wiring layer and the first semiconductor chip in a horizontal direction are substantially the same. A width of the second wiring layer and the second semiconductor chip in the horizontal direction are substantially the same. A height of the first via and the first semiconductor chip in the vertical direction are substantially the same.

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