公开(公告)号：US20250014958A1

公开(公告)日：2025-01-09

申请号：US18892965

申请日：2024-09-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeonggi Jin ,  Jumyong Park ,  Jinho An ,  Taehwa Jeong ,  Jinho Chun ,  Juil Choi ,  Atsushi Fujisaki

IPC: H01L23/31 ,  H01L23/29 ,  H01L23/522

Abstract: A semiconductor package includes: a lower package including a lower semiconductor chip, a molding layer on a side surface of the lower semiconductor chip, a conductive post in the molding layer and having a concave top surface, a lower redistribution pattern electrically connecting the lower semiconductor chip to the conductive post, and an upper redistribution electrically connected the conductive post; and an upper package on the lower package, the upper package including an upper semiconductor chip. A first portion of an inner wall of the molding layer contacts a sidewall of the conductive post, and a second portion of the inner wall of the molding layer extends vertically above the top surface of the conductive post, wherein the first and second portions of the inner wall of the molding layer are vertically coplanar with each other and with the sidewall of the conductive post.

公开(公告)号：US11996358B2

公开(公告)日：2024-05-28

申请号：US17364558

申请日：2021-06-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-Il Choi ,  Jumyong Park ,  Jin Ho An ,  Dongjoon Oh ,  Chungsun Lee ,  Jeonggi Jin ,  Jinho Chun

IPC: H01L23/498

CPC classification number: H01L23/49838 ,  H01L23/49822

Abstract: A semiconductor package includes a redistribution substrate that includes a first redistribution pattern and a second redistribution pattern that are at different levels from each other, and a semiconductor chip on the redistribution substrate and including a plurality of chip pads electrically connected to the first and second redistribution patterns. The first redistribution pattern includes a first metal pattern on a first dielectric layer, and a first barrier pattern between the first dielectric layer and a bottom surface of the first metal pattern. The second redistribution pattern includes a second metal pattern in a second dielectric layer, and a second barrier pattern between the second dielectric layer and a bottom surface of the second metal pattern and between the second dielectric layer and a sidewall of the second metal pattern.

公开(公告)号：US11984420B2

公开(公告)日：2024-05-14

申请号：US18074134

申请日：2022-12-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeonggi Jin ,  Solji Song ,  Taehwa Jeong ,  Jinho Chun ,  Juil Choi ,  Atsushi Fujisaki

IPC: H01L23/00 ,  H01L23/522

CPC classification number: H01L24/14 ,  H01L23/5226 ,  H01L2224/13008 ,  H01L2224/13009 ,  H01L2224/13166 ,  H01L2224/13171 ,  H01L2224/13184 ,  H01L2224/16146

Abstract: A semiconductor package including a semiconductor chip, a redistribution layer structure disposed under the semiconductor chip, a bump pad disposed under the redistribution layer structure and having an upper structure of a first width and a lower structure of a second width less than the first width, a metal seed layer disposed along a lower surface of the upper structure and a side surface of the lower structure, an insulating layer surrounding the redistribution layer structure and the bump pad, and a bump structure disposed under the bump pad. A first undercut is disposed at one end of the metal seed layer that contacts the upper structure, and a second undercut is disposed at an other end of the metal seed layer that contacts the lower structure.

公开(公告)号：US09530706B2

公开(公告)日：2016-12-27

申请号：US14669291

申请日：2015-03-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Pil-Kyu Kang ,  Byung Lyul Park ,  Taeyeong Kim ,  Yeun-Sang Park ,  Dosun Lee ,  Ho-Jin Lee ,  Jinho Chun ,  Ju-il Choi ,  Yi Koan Hong

IPC: H01L25/065 ,  H01L21/66 ,  H01L25/00 ,  H01L23/00 ,  H01L25/18 ,  H01L21/768 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L25/50 ,  H01L21/304 ,  H01L21/561 ,  H01L21/76898 ,  H01L22/32 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/08146 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06558 ,  H01L2225/06565 ,  H01L2225/06596 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A semiconductor device having a chip stack and an interconnection terminal is provided. The chip stack includes a first semiconductor chip, a second semiconductor chip and a third semiconductor chip stacked on each other. The interconnection terminal is electrically coupled to the chip stack. The first semiconductor chip includes a first front surface and a first backside surface. The second semiconductor chip includes a second front surface, a second backside surface, a second circuit layer and a through-electrode which is electrically coupled to the second circuit layer and penetrates the second semiconductor chip. The third semiconductor chip includes a third front surface, a third backside surface opposite to the third front surface and a third circuit layer adjacent to the third front surface. The first front surface and the second front surface face each other. The third front surface and the second backside surface face each other.

Abstract translation: 提供具有芯片堆叠和互连端子的半导体器件。 芯片堆叠包括彼此堆叠的第一半导体芯片，第二半导体芯片和第三半导体芯片。 互连端子电耦合到芯片堆叠。 第一半导体芯片包括第一正面和第一背面。 第二半导体芯片包括电耦合到第二电路层并穿透第二半导体芯片的第二前表面，第二背面，第二电路层和贯通电极。 第三半导体芯片包括第三前表面，与第三前表面相对的第三背面和与第三前表面相邻的第三电路层。 第一前表面和第二前表面彼此面对。 第三前表面和第二后侧表面彼此面对。

公开(公告)号：US11978688B2

公开(公告)日：2024-05-07

申请号：US17966864

申请日：2022-10-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jumyong Park ,  Solji Song ,  Jinho An ,  Jeonggi Jin ,  Jinho Chun ,  Juil Choi

IPC: H01L29/40 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L21/3105 ,  H01L21/321 ,  H01L23/29

CPC classification number: H01L23/3192 ,  H01L21/76898 ,  H01L23/3171 ,  H01L23/481 ,  H01L24/05 ,  H01L21/31053 ,  H01L21/3212 ,  H01L23/293 ,  H01L2224/05025 ,  H01L2224/05073 ,  H01L2224/0557 ,  H01L2224/05573

Abstract: A semiconductor device is disclosed. The semiconductor device includes a via passivation layer disposed on an inactive surface of a substrate, a through-electrode vertically penetrating the substrate and the via passivation layer, a concave portion formed in the top surface of the via passivation layer and disposed adjacent to the through-electrode, and a via protective layer coplanar with the via passivation layer and the through-electrode and to fill the concave portion. In a horizontal cross-sectional view, the via protective layer has a band shape surrounding the through-electrode.

公开(公告)号：US20170053882A1

公开(公告)日：2017-02-23

申请号：US15209298

申请日：2016-07-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeonggi Jin ,  Kyu-Ha Lee ,  Jinho Chun ,  Byunglyul Park ,  Jinho An

IPC: H01L23/00 ,  H01L25/00 ,  H01L21/78 ,  H01L23/31 ,  H01L25/11

CPC classification number: H01L24/09 ,  H01L21/4857 ,  H01L21/78 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/525 ,  H01L24/05 ,  H01L24/08 ,  H01L25/117 ,  H01L25/50 ,  H01L2224/0231 ,  H01L2224/0233 ,  H01L2224/02351 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/06181 ,  H01L2224/08059 ,  H01L2224/08111 ,  H01L2224/13022 ,  H01L2224/17181 ,  H01L2225/0652 ,  H01L2225/06541

Abstract: An electronic device includes an upper insulating layer on a substrate. An upper redistribution structure is embedded in the upper insulating layer. The upper redistribution structure includes an upper contact portion, an upper pad portion, and an upper line portion between the upper contact portion and the upper pad portion. A passivation layer is on the upper insulating layer and the upper redistribution structure. An upper opening is configured to pass through the passivation layer and expose the upper pad portion. Vertical thicknesses of the upper pad portion and the upper contact portion are greater than a vertical thickness of the upper line portion.

Abstract translation: 电子器件包括在衬底上的上绝缘层。 上部再分配结构嵌入在上绝缘层中。 上再分配结构包括上接触部分，上焊盘部分和上接触部分和上焊盘部分之间的上线部分。 钝化层位于上绝缘层和上再分布结构上。 上开口构造成穿过钝化层并暴露上焊盘部分。 上部焊盘部分和上部接触部分的垂直厚度大于上部分部分的垂直厚度。

公开(公告)号：US20240266309A1

公开(公告)日：2024-08-08

申请号：US18637061

申请日：2024-04-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeonggi Jin ,  Solji Song ,  Taehwa Jeong ,  Jinho Chun ,  Juil Choi ,  Atsushi Fujisaki

IPC: H01L23/00 ,  H01L23/522

CPC classification number: H01L24/14 ,  H01L23/5226 ,  H01L2224/13008 ,  H01L2224/13009 ,  H01L2224/13166 ,  H01L2224/13171 ,  H01L2224/13184 ,  H01L2224/16146

Abstract: A semiconductor package including a semiconductor chip, a redistribution layer structure disposed under the semiconductor chip, a bump pad disposed under the redistribution layer structure and having an upper structure of a first width and a lower structure of a second width less than the first width, a metal seed layer disposed along a lower surface of the upper structure and a side surface of the lower structure, an insulating layer surrounding the redistribution layer structure and the bump pad, and a bump structure disposed under the bump pad. A first undercut is disposed at one end of the metal seed layer that contacts the upper structure, and a second undercut is disposed at an other end of the metal seed layer that contacts the lower

公开(公告)号：US20210035878A1

公开(公告)日：2021-02-04

申请号：US16829227

申请日：2020-03-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeonggi Jin ,  Jumyong Park ,  Jinho An ,  Taehwa Jeong ,  Jinho Chun ,  Juil Choi ,  Atsushi Fujisaki

IPC: H01L23/31 ,  H01L23/29 ,  H01L23/522

Abstract: A semiconductor package includes a semiconductor chip including a chip pad; a lower redistribution structure on the semiconductor chip, the lower redistribution structure including a lower redistribution insulating layer and a lower redistribution pattern electrically connected to the chip pad of the semiconductor chip; a molding layer on at least a portion of the semiconductor chip; and a conductive post in the molding layer, the conductive post having a bottom surface and a top surface, the bottom surface of the conductive post being in contact with the lower redistribution pattern of the lower redistribution structure and the top surface of the conductive post having a concave shape.

公开(公告)号：US09799619B2

公开(公告)日：2017-10-24

申请号：US15209298

申请日：2016-07-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeonggi Jin ,  Kyu-Ha Lee ,  Jinho Chun ,  Byunglyul Park ,  Jinho An

IPC: H01L23/00 ,  H01L23/31 ,  H01L25/11 ,  H01L21/78 ,  H01L25/00

CPC classification number: H01L24/09 ,  H01L21/4857 ,  H01L21/78 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/525 ,  H01L24/05 ,  H01L24/08 ,  H01L25/117 ,  H01L25/50 ,  H01L2224/0231 ,  H01L2224/0233 ,  H01L2224/02351 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/06181 ,  H01L2224/08059 ,  H01L2224/08111 ,  H01L2224/13022 ,  H01L2224/17181 ,  H01L2225/0652 ,  H01L2225/06541

Abstract: An electronic device includes an upper insulating layer on a substrate. An upper redistribution structure is embedded in the upper insulating layer. The upper redistribution structure includes an upper contact portion, an upper pad portion, and an upper line portion between the upper contact portion and the upper pad portion. A passivation layer is on the upper insulating layer and the upper redistribution structure. An upper opening is configured to pass through the passivation layer and expose the upper pad portion. Vertical thicknesses of the upper pad portion and the upper contact portion are greater than a vertical thickness of the upper line portion.

公开(公告)号：US12142541B2

公开(公告)日：2024-11-12

申请号：US16829227

申请日：2020-03-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeonggi Jin ,  Jumyong Park ,  Jinho An ,  Taehwa Jeong ,  Jinho Chun ,  Juil Choi ,  Atsushi Fujisaki

IPC: H01L23/31 ,  H01L23/29 ,  H01L23/522

Abstract: A semiconductor package includes a semiconductor chip including a chip pad; a lower redistribution structure on the semiconductor chip, the lower redistribution structure including a lower redistribution insulating layer and a lower redistribution pattern electrically connected to the chip pad of the semiconductor chip; a molding layer on at least a portion of the semiconductor chip; and a conductive post in the molding layer, the conductive post having a bottom surface and a top surface, the bottom surface of the conductive post being in contact with the lower redistribution pattern of the lower redistribution structure and the top surface of the conductive post having a concave shape.