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公开(公告)号:US10538843B2
公开(公告)日:2020-01-21
申请号:US15385006
申请日:2016-12-20
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Hyun-Sik Sim , Jung-Suk Oh , Jae-Seok Kim , Ho-Gon Kim , Jun-Won Lee , Hyuk-Yul Choi , Hyung-Ho Kim , Sang-Jin Choi , Heok-Jae Lee , Dong-Ok Shin , Jang-Hyoun Youm , Ichiro Nishikawa , Masanori Terasaka , Masashi Hamada , Tae-Hoon Lee
IPC: C23C16/455 , C23C16/44
Abstract: A vaporizer includes a main body including a first body and a second body. The first body has an upper portion narrowing in a direction of a height of the first body and the second body has a cavity in which the first body is positioned. A mixing chamber is between the first and second bodies. The second body includes a carrier gas injection path connected to a carrier gas inlet formed in an upper portion of the mixing chamber. The carrier gas injection path carries a carrier gas. A source material injection path is connected to a source material inlet formed in the mixing chamber. The source material injection path carries a liquid source material. A discharge is connected to an outlet formed in a lower portion of the mixing chamber. A mixed fluid including the carrier gas and the liquid source material is discharged through the discharge path.
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公开(公告)号:USD841646S1
公开(公告)日:2019-02-26
申请号:US29617105
申请日:2017-09-12
Applicant: Samsung Electronics Co., Ltd.
Designer: Hyun-Keun Son , Jun-Won Lee , Jang-Woon Kim , Chung-Ha Kim , Jae-Ho Baik , Seung-Ho Jang
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公开(公告)号:US11737256B2
公开(公告)日:2023-08-22
申请号:US17476663
申请日:2021-09-16
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jun-Won Lee , Hyuk-Woo Kwon , Ik-Soo Kim , Byoung-Deog Choi
IPC: H10B12/00 , H01L21/768 , H01L21/311 , H01L21/02 , H01L21/8234
CPC classification number: H10B12/03 , H01L21/02126 , H01L21/02129 , H01L21/02131 , H01L21/02164 , H01L21/311 , H01L21/76802 , H01L21/76877 , H01L21/823468 , H10B12/0335 , H10B12/30
Abstract: A semiconductor device and a method of manufacturing a semiconductor device, the device including a substrate; a lower structure including pad patterns on the substrate, upper surfaces of the pad patterns being at an outer side of the lower structure; a plurality of lower electrodes contacting the upper surfaces of the pad patterns; a dielectric layer and an upper electrode sequentially stacked on a surface of each of the lower electrodes; and a hydrogen supply layer including hydrogen, the hydrogen supply layer being between the lower electrodes and closer to the substrate than the dielectric layer is to the substrate.
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公开(公告)号:US10459493B2
公开(公告)日:2019-10-29
申请号:US16004725
申请日:2018-06-11
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jun-Won Lee , Jang-Woon Kim , Chung-Ha Kim , Jae-Ho Baik , Hyun-Keun Son , Seung-Ho Jang
Abstract: An electronic device according to one embodiment may include: a first housing including a first side; a second housing including a second side facing the first side; at least one first magnetic member configured to be rotatably disposed inside the first housing and adjacent to the first side; and at least one second magnetic member configured to be rotatably disposed inside the second housing and adjacent to the second side, wherein the first housing and the second housing are rotatably coupled to each other by a magnetic force between the at least one first magnetic member and the at least one second magnetic member. Various other embodiments are also possible.
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公开(公告)号:US10892263B2
公开(公告)日:2021-01-12
申请号:US16270865
申请日:2019-02-08
Applicant: Samsung Electronics Co., Ltd.
Inventor: Hoi Sung Chung , Tae Sung Kang , Dong Suk Shin , Kong Soo Lee , Jun-Won Lee
IPC: H01L21/336 , H01L27/092 , H01L21/8238 , H01L29/78 , H01L27/108 , H01L21/265 , H01L29/66 , H01L21/02 , H01L21/768 , H01L29/51 , H01L21/311 , H01L21/324 , H01L29/08 , H01L29/40 , H01L21/266 , H01L29/04
Abstract: Methods of fabricating a semiconductor device are provided. The methods may include forming a gate structure on a core-peri region of a substrate. The substrate may further include a cell region. The methods may also include forming a gate spacer on a sidewall of the gate structure, forming a first impurity region adjacent the gate spacer in the core-peri region of the substrate by performing a first ion implantation process, removing the gate spacer, forming a second impurity region in the core-peri region of the substrate between the gate structure and the first impurity region by performing a second ion implantation process, forming a stress film on the gate structure, an upper surface of the first impurity region, and an upper surface of the second impurity region, and forming a recrystallization region by crystallizing the first impurity region and the second impurity region by performing an annealing process.
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公开(公告)号:US10586709B2
公开(公告)日:2020-03-10
申请号:US16030212
申请日:2018-07-09
Applicant: Samsung Electronics Co., Ltd.
Inventor: Young-Min Ko , Hyuk Woo Kwon , Jun-Won Lee
IPC: H01L21/308 , G03F7/20 , H01L21/033 , H01L21/02 , H01L21/3213 , H01L21/311
Abstract: Methods for fabricating a semiconductor device are provided including sequentially forming a first hard mask layer, a second hard mask layer and a photoresist layer on a target layer, patterning the photoresist layer to form a photoresist pattern, sequentially patterning the second hard mask layer and the first hard mask layer using the photoresist pattern as an etching mask to form a first hard mask pattern and a second hard mask pattern on the first hard mask pattern, and etching the target layer using the first hard mask pattern and the second hard mask pattern as an etching mask, wherein the second hard mask layer includes impurity-doped amorphous silicon.
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公开(公告)号:US10573652B2
公开(公告)日:2020-02-25
申请号:US15945401
申请日:2018-04-04
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Myeong-Dong Lee , Jun-Won Lee , Ki Seok Lee , Bong-Soo Kim , Seok Han Park , Sung Hee Han , Yoo Sang Hwang
IPC: H01L27/108 , H01L23/532 , H01L23/522 , H01L23/528
Abstract: A semiconductor device includes a substrate having a trench, a bit line in the trench, a first spacer extending along the trench and at least a portion of a side surface of the bit line and in contact with the bit line, and a second spacer disposed within the trench on the first spacer. The bit line is narrower than the trench, and the first spacer includes silicon oxide. A method of forming a semiconductor device includes forming a trench in a substrate, forming a bit line within the first trench of width less than that of the first trench, and forming a first spacer that lines a portion of the trench and includes silicon oxide in contact with at least a portion of a side surface of the bit line, and forming a second spacer over the first spacer in the trench.
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公开(公告)号:US11133317B2
公开(公告)日:2021-09-28
申请号:US16420387
申请日:2019-05-23
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jun-Won Lee , Hyuk-Woo Kwon , Ik-Soo Kim , Byoung-Deog Choi
IPC: H01L27/108 , H01L21/768 , H01L21/311 , H01L21/02 , H01L21/8234
Abstract: A semiconductor device and a method of manufacturing a semiconductor device, the device including a substrate; a lower structure including pad patterns on the substrate, upper surfaces of the pad patterns being at an outer side of the lower structure; a plurality of lower electrodes contacting the upper surfaces of the pad patterns; a dielectric layer and an upper electrode sequentially stacked on a surface of each of the lower electrodes; and a hydrogen supply layer including hydrogen, the hydrogen supply layer being between the lower electrodes and closer to the substrate than the dielectric layer is to the substrate.
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公开(公告)号:USD840394S1
公开(公告)日:2019-02-12
申请号:US29617109
申请日:2017-09-12
Applicant: Samsung Electronics Co., Ltd.
Designer: Hyun-Keun Son , Jun-Won Lee , Jang-Woon Kim , Chung-Ha Kim , Seung-Ho Jang
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公开(公告)号:USD840393S1
公开(公告)日:2019-02-12
申请号:US29617102
申请日:2017-09-12
Applicant: Samsung Electronics Co., Ltd.
Designer: Chung-Ha Kim , Jang-Woon Kim , Hyun-Keun Son , Jun-Won Lee , Seung-Ho Jang
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